Subthreshold leakage power reduction in VLSI circuits: A survey

2016 ◽  
Author(s):  
K Sridhara ◽  
G S Biradar ◽  
Raju Yanamshetti
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Subthreshold Leakage

scholarly journals Leakage Power Reduction in CMOS VLSI Circuits

2012 ◽  
Vol 55 (8) ◽  
pp. 42-48 ◽  
Author(s):  
Pushpa Saini ◽  
Rajesh Mehra
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Cmos Vlsi

A New Leakage Power Reduction Technique for CMOS VLSI Circuits

2012 ◽  
Vol 5 (4) ◽  
pp. 227-232 ◽  
Author(s):  
M. Geetha Priya ◽  
K. Baskaran ◽  
D. Krishnaven ◽  
S. Srinivasan
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Reduction Technique ◽  
Vlsi Circuits ◽  
Cmos Vlsi

scholarly journals Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

2017 ◽  
Vol 14 (1) ◽  
pp. 74 ◽  
Author(s):  
B. Kalagadda ◽  
N. Muthyala ◽  
K.K. Korlapati
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Digital Circuit ◽  
Performance Comparison ◽  
Power Reduction ◽  
Leakage Power ◽  
Nand Gate ◽  
Reduction Techniques ◽  
Half Adder ◽  
Subthreshold Leakage

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation. 

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