Enhanced All-Optical Y-Shaped Plasmonic OR, NOR And NAND Gate Models, Analyses, And Simulation For High Speed Computations

In this digital era, all-optical logic gates (OLGs) proved its effectiveness in execution of high-speed computations. A unique construction of an all-optical OR, NOR, NAND gates based on the notion of power combiner employing metal–insulator–metal (MIM) waveguide in the Y-shape in a minimal imprint of 6.2 µm × 3 µm is presented and the structure is evaluated by finite-difference time-domain (FDTD) technique. The insertion loss (IL) and extinction-ratio (ER) for proposed model are 6 dB and 27.76 dB for NAND gate, 2 dB and 20.35 dB for NOR gate and 6 dB and 24.10 dB respectively. The simplified model is used in the construction of complex circuits to achieve greater efficiency, which contributes to the emergence of a new technique for designing plasmonic integrated circuits.

Simulation of the characteristics of low-voltage gates on combined cylindrical surrounding gate field-effect nanotransistors

The applicability of the architecture of a nanoscale surrounding gate field-effect transistor with a combined cylindrical working area for low-voltage applications is discussed. At the same time, the licensed TCAD Sentaurus instrument and technological modeling system is used as a tool. The transistor architecture under consideration involves combining the working zones of n-channel and p-channel transistors with one common gate. At the same time, the efficiency of suppressing short-channel effects is maintained and a high level of transistor current is provided in the strong inversion mode. Based on this architecture, a TCAD model of the NAND gate has been developed, the design of which contains two independent surrounding gates one combined working area. The use of the proposed gate architecture makes it possible to reduce the number of required transistor structures per gate by three times. This leads to a decrease in the switched capacity and power dissipation. From the simulation results, the gate geometric parameters with a working area length of 25 nm and a diameter of 8.5 nm, which can function at control voltages of 0.5 V in the frequency range up to 20 GHz with high gain, are determined. The switching time delay is 0.81 ps. The TCAD model of a half-adder is developed in the basis 2NAND. According to the simulation results, the efficiency of the prototype, which performs binary code addition operations with a delay of 4.2 ps at a supply voltage of 0.5 V and a frequency of 20 GHz, is shown. The obtained results create a theoretical basis for the synthesis of low-voltage complex functional blocks with high performance and minimal occupied area, which meets modern requirements for digital applications.

All-Optical Universal Logic Gates at Nano-scale Dimensions

Though photonics displays an attractive solution to the speed limitation of electronics, decreasing the size of photonic devices is one of the major problems with implementing photonic integrated circuits that are regarded the challenges to produce all-optical computers. Plasmonic can solve these problems, it be a potential solution to fill the gaps in the electronics (large bandwidth and ultra-high speed) and photonics (diffraction limit due to miniaturization size). In this paper, Nano-rings Insulator-Metal-Insulator (IMI) plasmonic waveguides has been used to propose, design, simulate, and perform all-optical universal logic gates (NOR and NAND gates). By using Finite Element Method (FEM), the structure of the proposed plasmonic universal logic gates are designed and numerically simulated by two dimensions (2-D) structure. Silver and Glass materials were chosen to construct proposed structure. The function of the proposed plasmonic NOR and NAND logic gates was achieved by destructive and constructive interferences principle. The performance of the proposed device is measured by three criteria; the transmission, extension ratio, and modulation depth. Numerical simulations show that a transmission threshold (0.3) which allows achieving the proposed plasmonic universal logic gates in one structure at 1550 nm operating wavelength. The properties of this devise was as follows: The transmission exceeds 100% in one state of NAND gate, medium values of Extension Ratio, very high MD values, and very small foot print. In the future, this device will be the access to the nanophotonic integrated circuits and it has regarded fundamental building blocks for all-optical computers.

FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design

In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, and the circuit of AND gate and OR gate composed of memristors is built by using this model. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has obvious advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

Enhanced All-optical Y-shaped Plasmonic NAND Gate Model, Analysis, and Simulation for High Speed Computations

In this digital era, all-optical logic gates (OLGs) proved its effectiveness in execution of high-speed computations. A unique construction for all optical NAND gate based on the notion of power combiner employing metal–insulator–metal (MIM) waveguide in the Y-shape in a minimal imprint of 6.2 µm × 3 µm is presented and the structure is evaluated by finite-difference time-domain (FDTD) technique. The insertion loss (IL) and extinction-ratio (ER) for proposed model are 6 dB and 27.76 dB. The simplified model is used in the construction of complex circuits to achieve greater efficiency, which contributes to the emergence of a new technique for designing plasmonic integrated circuits.

A High-Speed Bidirectional Register with Parallel Loading using single electron Threshold Logic Technology

In this work we have concentrated our attention to a High Speed 4-bit Bidirectional Register with Parallel Loading counting on the principle of threshold logic gates (TLG). After determining the number of logic gates and other circuits needed to complete the desired circuit for our work, we implement some gates and circuits made up of tunnel junctions and capacitances. Some multi-inputs (greater than two) are designed or implemented with the assistance of modified version of the generic multi-input TLG. The types of gates suitable for the implementing the bidirectional Register are 3-input AND, 3-input NAND and 4-input OR gates, in addition an inverter and a more complex circuits like 4:1 Multiplexer are the part and parcel of the desired device. With the help of a 3-input AND gate and a 4-input OR gate, a 4:1 Multiplexer is built. By using the 3-input NAND gate a memory element – D Flip-flop is constructed. At last 4 number of 4:1 Multiplexers and another four number of D Flip-flops are combined in a parallel pattern to implement a 4-bit Bidirectional Register with Parallel Loading. Each component is made after analyzing their corresponding threshold linear equations. After constructing the threshold circuits, again they are formed by using the parameters as capacitors, tunnel junctions with their internal resistances. All the circuit, which are constructed, are verified by simulation with the help of SIMON and the result obtained are investigated and found that they are matched with the theoretical results. For comparing the fastness of our circuit with the CMOS-based or single electron transistor (SET) based circuit, the processing delays of all gates/ circuits are determined. How much power they consume are measured as well. Comparing the delays of CMOS-based and SET based circuit with the TLG based circuit we have decided that our 4-bit Bidirectional Register with Parallel Loading is speedier.

Simulation Analysis of Circuit and Designing of PCB Layout of a CMOS based NAND Logic Gate using Open-Source Software eSim

A real world signals are mostly based on Boolean operators. In simple language Boolean operators are logic gates and logic gates are the building blocks of any circuit. There are different types of logic gates like AND, OR, NOT, NAND, NOR, XOR, and XNOR. These all-logic gates are implemented using a Boolean function. And all these logic gates internally are implemented using diodes and transistors. And when we implement all these logic gates using transistor and diodes then it comes under logic families. In this paper we are going to do the analysis of NAND GATE using CMOS in 180 nm technology and has also designed its PCB layout. We are going to carried out the whole simulation of the proposed design of NAND Gate in eSim (Electronic Simulation) Software which is an EDA tool. And by changing the different values of inputs of NAND Gate we are observing respective output in simulation process of eSim.

Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit