2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
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Published By IEEE

9781509000333

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A RISC-V instruction set processor-micro-architecture design and analysis

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593047 ◽

2016 ◽

Cited By ~ 5

Author(s):

Aneesh Raveendran ◽

Vinayak Baramu Patil ◽

David Selvakumar ◽

Vivian Desalphine

Keyword(s):

Architecture Design ◽

Instruction Set

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Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593036 ◽

2016 ◽

Author(s):

S. Poorvasha ◽

B. Lakshmi

Keyword(s):

Gate Oxide ◽

Double Gate ◽

Tunnel Fets

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Effect on temperature and time in parallel test scheduling with alterations in layers arrangements of 3D stacked SoCs

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593029 ◽

2016 ◽

Author(s):

Indira Rawat ◽

M. K. Gupta ◽

Virendra Singh

Keyword(s):

Test Scheduling ◽

Parallel Test

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Design and analysis of novel fuzzifer circuits in CMOS current mode approach

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593035 ◽

2016 ◽

Author(s):

Abdullah Gubbi ◽

M. Deeksha

Keyword(s):

Current Mode

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Design of 3C-SiC symmetric and asymmetric double gate MOSFET

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593052 ◽

2016 ◽

Author(s):

Sudarshana Jilowa ◽

Sandeep Singh Gill ◽

Gurjot Kaur Walia

Keyword(s):

Double Gate ◽

Double Gate Mosfet

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Reconfigurable side channel attack resistant true random number generator

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593048 ◽

2016 ◽

Cited By ~ 3

Author(s):

Vijay Bahadur ◽

David Selvakumar ◽

Vijendran ◽

P. M. Sobha

Keyword(s):

Random Number ◽

Random Number Generator ◽

Side Channel ◽

Number Generator ◽

Side Channel Attack ◽

True Random Number Generator

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Towards formal verification of adaptive cruise controller using SpaceEx

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593042 ◽

2016 ◽

Author(s):

Ambuj Mishra ◽

Subir K Roy

Keyword(s):

Formal Verification

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Efficient Network on Chip (NoC) using heterogeneous circuit switched routers

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593043 ◽

2016 ◽

Cited By ~ 1

Author(s):

Anuja Naik ◽

Tirumale K. Ramesh

Keyword(s):

Network On Chip ◽

On Chip

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FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593025 ◽

2016 ◽

Cited By ~ 2

Author(s):

Satish S Bhairannawar ◽

Rajath Kumar ◽

Varsha Mirji ◽

P S Sindhu

Keyword(s):

Face Recognition ◽

Lifting Scheme ◽

Recognition System ◽

Fpga Implementation ◽

Face Recognition System

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A circuit technique for leakage power reduction in CMOS VLSI circuits

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593044 ◽

2016 ◽

Author(s):

Venkata Ramakrishna Nandyala ◽

Kamala Kanta Mahapatra

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Vlsi Circuits ◽

Cmos Vlsi ◽

Circuit Technique

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2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A RISC-V instruction set processor-micro-architecture design and analysis

Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs

Effect on temperature and time in parallel test scheduling with alterations in layers arrangements of 3D stacked SoCs

Design and analysis of novel fuzzifer circuits in CMOS current mode approach

Design of 3C-SiC symmetric and asymmetric double gate MOSFET

Reconfigurable side channel attack resistant true random number generator

Towards formal verification of adaptive cruise controller using SpaceEx

Efficient Network on Chip (NoC) using heterogeneous circuit switched routers

FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme

A circuit technique for leakage power reduction in CMOS VLSI circuits

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
Latest Publications