ON chip LDO voltage regulator with improved transient response in 180nm

Author(s):  
Patri Sreehari Rao ◽  
K.S.R. Krishna Prasad
Author(s):  
Hatim Ameziane ◽  
Kamal Zared ◽  
Hicham Akhamal ◽  
Hassan Qjidaa

<span>A full on chip low Dropout Voltage Regulator (LDO) with fast transient response and small capacitor compensation circuit is proposed. The novel technique is implemented to detect the variation voltage at the output of LDO and enable the proposed fast detector amplifier (FDA) to improve load transient response of 50mA load step. The large external capacitor used in Conventional LDO Regulators is removed allowing for greater power system integration for system-on-chip (SoC) applications. The 1.6-V Full On-Chip LDO voltage regulator with a power supply of 1.8 V was designed and simulated in the 0.18µm CMOS technology, consuming only 14 µA of ground current with a fast settling-time LNR(Line Regulation) and LOR(Load regulation) of 928ns and 883ns respectively while the rise and fall times in LNR and LOR is 500ns.</span>


2009 ◽  
Vol 18 (07) ◽  
pp. 1263-1285 ◽  
Author(s):  
GUOQING CHEN ◽  
EBY G. FRIEDMAN

With higher operating frequencies, transmission lines are required to model global on-chip interconnects. In this paper, an accurate and efficient solution for the transient response at the far end of a transmission line based on a direct pole extraction of the system is proposed. Closed form expressions of the poles are developed for two special interconnect systems: an RC interconnect and an RLC interconnect with zero driver resistance. By performing a system conversion, the poles of an interconnect system with general circuit parameters are solved. The Newton–Raphson method is used to further improve the accuracy of the poles. Based on these poles, closed form expressions for the step and ramp response are determined. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. With two pairs of poles, the average error of the 50% delay is 1% as compared with Spectre simulations. With ten pairs of poles, the average error of the 10%-to-90% rise time and the overshoots is 2% and 1.9%, respectively. Frequency dependent effects are also successfully included in the proposed method and excellent match is observed between the proposed model and Spectre simulations.


2019 ◽  
Vol 27 (8) ◽  
pp. 1768-1778 ◽  
Author(s):  
Venkata Chaitanya Krishna Chekuri ◽  
Monodeep Kar ◽  
Arvind Singh ◽  
Saibal Mukhopadhyay
Keyword(s):  

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