scholarly journals Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems

2019 ◽  
Vol 9 (6) ◽  
pp. 4637 ◽  
Author(s):  
Hatim Ameziane ◽  
Kamal Zared ◽  
Hicham Akhamal ◽  
Hassan Qjidaa
Keyword(s):  
Power Systems ◽  
Transient Response ◽  
System Integration ◽  
Cmos Technology ◽  
Voltage Regulator ◽  
Fast Transient Response ◽  
Ground Current ◽  
Load Regulation ◽  
On Chip ◽  
Fast Settling

<span>A full on chip low Dropout Voltage Regulator (LDO) with fast transient response and small capacitor compensation circuit is proposed. The novel technique is implemented to detect the variation voltage at the output of LDO and enable the proposed fast detector amplifier (FDA) to improve load transient response of 50mA load step. The large external capacitor used in Conventional LDO Regulators is removed allowing for greater power system integration for system-on-chip (SoC) applications. The 1.6-V Full On-Chip LDO voltage regulator with a power supply of 1.8 V was designed and simulated in the 0.18µm CMOS technology, consuming only 14 µA of ground current with a fast settling-time LNR(Line Regulation) and LOR(Load regulation) of 928ns and 883ns respectively while the rise and fall times in LNR and LOR is 500ns.</span>

scholarly journals Hybrid Feedback Compensation of an External Capacitor-less Low Dropout Voltage Regulator

2014 ◽  
Vol 1 (1) ◽  
Author(s):  
Daniel Gitzel ◽  
Jose Silva-Martinez ◽  
Rafael Rivera
Keyword(s):  
Power Management ◽  
System Integration ◽  
Full Range ◽  
Cmos Technology ◽  
Voltage Regulator ◽  
Fast Transient Response ◽  
Feedback Compensation ◽  
Active Feedback ◽  
Alternative Topology ◽  
Stability Issues

Power management has an ever increasing presence in the electronics industry due to the growth of battery powered mobile devices. The low-dropout voltage regulator (LDO) offers improved efficiency over other regulator topologies. However, the architecture suffers from stability issues, which usually necessitates a large off-chip capacitor to ensure the regulator’s performance. This paper presents an alternative topology by removing the bulky external capacitor, thus allowing for greater power system integration. The proposed Current Amplifier Hybrid Compensation (CAHC) scheme implements an active feedback-feedforward compensation system and maintains both a fast transient response and full range alternating current (AC) stability from 0 to 50mA load currents even with a 100pF loading capacitance. The 1.2V External Capacitor-less LDO voltage regulator was designed and simulated in a commercial 0.35um CMOS technology, consuming only 61uA of quiescent current with a dropout voltage of less than 200mV. Simulated results demonstrate that the proposed External Capacitor-less LDO architecture overcomes the typical load transient and AC stability issues encountered in previous architectures. The combined size and component reduction of this architecture presents a more integrable and economic power management system.

scholarly journals High-voltage circuits for power management on 65 nm CMOS

2015 ◽  
Vol 13 ◽  
pp. 109-120
Author(s):  
S. Pashmineh ◽  
D. Killat
Keyword(s):  
Power Management ◽  
Circuit Design ◽  
High Voltage ◽  
Cmos Technology ◽  
Buck Converter ◽  
Drop Out ◽  
Voltage Regulator ◽  
Error Amplifier ◽  
Load Regulation ◽  
Switching Characteristics

Abstract. This paper presents two high-voltage circuits used in power management, a switching driver for buck converter with optimized on-resistance and a low dropout (LDO) voltage regulator with 2-stacked pMOS pass devices. The circuit design is based on stacked MOSFETs, thus the circuits are technology independent. High-voltage drivers with stacked devices suffer from slow switching characteristics. In this paper, a new concept to adjust gate voltages of stacked transistors is introduced for reduction of on-resistance. According to the theory, a circuit is proposed that drives 2 stacked transistors of a driver. Simulation results show a reduction of the on-resistance between 27 and 86 % and a reduction of rise and fall times between 16 and 83 % with a load capacitance of 150 pF at various supply voltages, compared to previous work. The concept can be applied to each high-voltage driver that is based on a number (N) of stacked transistors. The high voltage compatibility of the low drop-out voltage regulator (LDO) is established by a 2-stacked pMOS transistors as pass device controlled by two regulators: an error amplifier and a 2nd amplifier adjusting the division of the voltages between the two pass transistors. A high GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. To improve stability, two feedback loops are utilized. In this paper, the 2.5 V I/O transistors of the TSMC 65 nm CMOS technology are used for the circuit design.

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