Effect of Ni barrier layer thickness on IMCs evolution in Ф5μm Cu/Ni/Sn pillar bumps

2018 ◽  
Author(s):  
Kai Chen ◽  
Huiqin Ling ◽  
Fayao Guo ◽  
Ming Li ◽  
Wenqi Zhang ◽  
...  
Keyword(s):  
Layer Thickness ◽  
Barrier Layer ◽  
Barrier Layer Thickness

Elastic-relaxation-induced barrier layer thickness undulations in InP/GaAs type-II quantum well superlattice structures

2012 ◽  
Vol 27 (10) ◽  
pp. 105031 ◽  
Author(s):  
S D Singh ◽  
Ravi Kumar ◽  
C Mukherjee ◽  
Pushpen Mondal ◽  
A K Srivastava ◽  
...  
Keyword(s):  
Quantum Well ◽  
Layer Thickness ◽  
Barrier Layer ◽  
Type Ii ◽  
Barrier Layer Thickness ◽  
Superlattice Structures

Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET

2018 ◽  
Vol 13 (10) ◽  
pp. 1473-1477 ◽  
Author(s):  
Sanjeev Kumar Sharma ◽  
Jeetendra Singh ◽  
Balwinder Raj ◽  
Mamta Khosla
Keyword(s):  
Layer Thickness ◽  
Barrier Layer ◽  
Significant Variation ◽  
Barrier Thickness ◽  
Gate Stack ◽  
Barrier Layer Thickness ◽  
Nanowire Mosfets ◽  
Silvaco Atlas ◽  
Nanowire Mosfet

In this paper, InGaAs/InP heterostructure based Cylindrical Gate Nanowire MOSFETs (CGNWMOSFET) is designed and its performance has been analyzed using silvaco ATLAS TCAD tool. The influence of the barrier thickness is investigated for perusal performance of an InGaAs/InP heterostructure CGNWMOSFET. The performance compared for various parameters on current, off current, Cut off Frequency (fT), Transconductance (gm), Gate to Source capacitance (Cgs), and Gate to Drain capacitance (Cgd). Results show significant variation in the performance of InGaAs/InP heterostructure CGNWMOSFET by varying the barrier thickness.

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