Simulation Study of Single-Event Burnout for the 4H-SiC VDMOSFET with N+ Split Source

Silicon Carbide (SiC) power MOSFET is the next generation device in the supply system of spacecraft. However, the current degradation or catastrophic failure of the power device could be induced when a drain voltage exceeds critical condition. In this article, an improved VDMOSFET structure for the Single-Event Burnout (SEB) is demonstrated. The improved power VDMOSFET includes a P+ shielding region at the JFET region. Meanwhile, forming a CSL layer by ion-implantation at the JFET to reduce the specific on-resistance. The device is etched in both sides to form trench and then implanting N-type impurities at the side walls of the trench to form the N+ split source (SDS-VDMOSFET). The 2-D numerical simulator Silvaco Atlas was used to study the SEB performance for the 1.2 kV-rated SiC SDS-VDMOSFET in a high linear energy transfer (LET) value of 0.5 pC/μm. The simulation results show that the improved structure can effectively reduce the peak lattice temperature induced by heavy-ion and increase the SEB threshold voltage compared with the standard VDMOSFET. Furthermore, the improved structure also presents a lower specific on-resistance. As a result, the maximum temperature of the standard VDMOSFET has exceeded 3000 K at a drain voltage of 400 V. However, the maximum temperature of the improved VDMOSFET is only 2090 K at a drain voltage of 800 V.

2D multifunctional SiAs2/GeAs2 van der waals heterostructure

The structural and electronic properties of two-dimensional (2D) SiAs2/GeAs2 van der Waals heterostructure (vdWH) and its applications are investigated by combing first-principles calculations and Silvaco Atlas simulations. The stable SiAs2/GeAs2 vdWH exhibits an indirect bandgap of 0.99 eV in type II band alignment for light detection and energy harvesting. The vdWH can exhibit a direct bandgap up to 0.66 eV by applying an appropriate electric field (Eext). Due to the Eext induced charge redistribution, its band alignment can be transformed from type II to type I for light-emitting. Further simulation shows that the band alignment of SiAs2/GeAs2 vdWH can be tuned back and forth between type II and type I by gate voltage in a single field-effect transistor for multiple functional applications. These results may be useful for applications of the SiAs2/GeAs2 heterostructure in future electronic and optoelectronic devices.

Simulation Study on the Effect of Doping Concentrations on the Photodetection Properties of Mg2Si/Si Heterojunction Photodetector

To develop and design an environmentally friendly, low-cost shortwave infrared (SWIR) photodetector (PD) material and extend the optical response cutoff wavelengths of existing silicon photodetectors beyond 1100 nm, high-performance silicon-compatible Mg2Si/Si PDs are required. First, the structural model of the Mg2Si/Si heterojunction was established using the Silvaco Atlas module. Second, the effects of the doping concentrations of Mg2Si and Si on the photoelectric properties of the Mg2Si/Si heterojunction PD, including the energy band, breakdown voltage, dark current, forward conduction voltage, external quantum efficiency (EQE), responsivity, noise equivalent power (NEP), detectivity, on/off ratio, response time, and recovery time, were simulated. At different doping concentrations, the heterojunction energy band shifted, and a peak barrier appeared at the conduction band of the Mg2Si/Si heterojunction interface. When the doping concentrations of Si and Mg2Si layer were 1017, and 1016 cm−3, respectively, the Mg2Si/Si heterojunction PD could obtain optimal photoelectric properties. Under these conditions, the maximum EQE was 70.68% at 800 nm, the maximum responsivity was 0.51 A/W at 1000 nm, the minimum NEP was 7.07 × 10−11 WHz–1/2 at 1000 nm, the maximum detectivity was 1.4 × 1010 Jones at 1000 nm, and the maximum on/off ratio was 141.45 at 1000 nm. The simulation and optimization result also showed that the Mg2Si/Si heterojunction PD could be used for visible and SWIR photodetection in the wavelength range from 400 to 1500 nm. The results also provide technical support for the future preparation of eco-friendly heterojunction photodetectors.

Reliability analysis of cost-efficient CH3NH3PbI3 based dopingless tunnel FET

Electrostatically-doped TFETs (ED-TFETs) are amongst the most widely used cost-efficient steeper devices due to the use of charge-plasma technique and tunneling mechanism. However, the reliability analysis of ED-TFETs has considered as an important concern for the research community. Also, most studies have only focused on improving the performance of ED-TFETs such as dopingless (DL)-TFET in terms of on-current (ION), subthreshold swing (SS) and threshold voltage (Vth) rather than investigating the reliability issues. In this context, the aim of our work is to investigate the reliability analysis of our previously reported methyl-ammonium lead tri-iodide materials based DL-TFET (MAPbI3-DL-TFET). The influence of interface trap charges, shallow and deep defects on the electrical and analog performance of MAPbI3-DL-TFET has been analyzed using Silvaco ATLAS tool at room temperature. Extensive results carried out show that deep-level (Gaussian) defects impact the performance of the device prominently while the tail defects affect the device performance insignificantly. The present findings showed that the donor/acceptor effect the device in subthreshold regime considerably, while in superthreshold regime the impact of trap charges is marginal. In our view, these result emphasizes the reliability analysis of MAPbI3-DL-TFET for the very first time. We hope that our research will be useful and valuable for DL-TFET manufacturers.

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog applications

In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

Study of Normally-Off AlGaN/GaN HEMT with Microfield Plate for Improvement of Breakdown Voltage

In this article, we introduce a new type of AlGaN/GaN high electron mobility transistor (HEMT) with microfield plate (FP). We use Silvaco-ATLAS two-dimensional numerical simulation to calculate the performance of conventional HEMT and HEMT with micro-FP and analyze its principle. By studying a new charge balance method provided by HEMTs and micro-FPs, the physical mechanism of FP adjusting the HEMT potential distribution and channel electric field distribution is analyzed. The new FP structure consists of a drain field plate (D-FP), a source field plate (S-FP) and several micro-gate field plates (G-FP) to improve the output characteristics of HEMTs. By adjusting the distribution of potential and channel electric field, a wider and more uniform channel electric field can be obtained, and the breakdown voltage can be increased to 1278 V. Although the on-resistance of the HEMT is slightly increased to 5.24 Ωmm, it is still lower than other reference values. These results may open up a new and effective method for manufacturing high-power devices for power electronics applications.

High Power Normally-OFF GaN/AlGaN HEMT with Regrown p Type GaN

In this paper is presented a Normally-OFF GaN HEMT (High Electron Mobility Transistor) device using p-doped GaN barrier layer regrown by CBE (Chemical Beam Epitaxy). The impact of the p doping on the device performance is investigated using TCAD simulator (Silvaco/Atlas). With 4E17 cm−3 p doping, a Vth of 1.5 V is achieved. Four terminal breakdowns of the fabricated device are investigated, and the origin of the device failure is identified.

Tfet Biosensor Simulation and Analysis for Various Biomolecules

This paper investigates the simulation and performance of Tunnel field effect transistor (TFET) with a nanocavity in it, which can be used for bio sensing application. The entire simulation is done using the tool Silvaco Atlas TCAD. This paper mainly aims in comparing the different parameters for few biomolecules which has different dielectric constant values, namely Streptavidin, Biotin, APTES, Cellulose and DNA. The device structure here consists of a nanocavity near the source end, which is used to place these biomolecules and hence observe the variation of the Drain current v/s Gate voltage characteristic graph, these biomolecules that are having unique dielectric constants are placed within this cavity and these graphs are observed. The energy band diagram of this device is obtained; on top of this various other parameters namely Surface Potential, Electric field are observed for the above-mentioned Biomolecules. The Length of the cavity of the biosensor is also varied to observe the difference, in addition to this Ion (ON current) variation is plotted for the change in the dielectric constant of the biomolecule.

Study And Investigation of Silicon Extended Source Vertical Double Gate Tunnel Transistor For Analog/RF Performance

In this paper, a Silicon Double Gate tunnel field effect transistor with Extended Source (ESVDG-TFET) is disclosed while addressing the need for dc/switching and analog/RF applications using Silvaco-Atlas simulator which is used to examine and explore the performance of the proposed device. The mechanics of band-to-band tunnelling and accompanying carrier injection are used to illustrate the operation of the proposed silicon ESVDG-TFET device. The gate is designed to overlap with extended source region along with N+ pockets and channel in order to facilitate both the lateral and vertical tunnelling . The silicon ESVDG-TFET provide lower subthreshold swing of 10.1 mV/decade that allow higher ratio of ION / IOFF of 1013 for optimized device structural parameters with threshold voltage of 0.35 V. Moreover, peak transconductance of 800 uS/ um, cutoff frequency of 82 GHz, gain bandwidth product of 16.8 GHz and transit time of 1p sec is obtained by proposed device.