Low Area and High Throughput Architectures of FIR Filter for Data Streaming DSP Applications

2021 ◽  
Author(s):  
Mahendra Vucha ◽  
Koppula Srinivas Rao ◽  
V Arun
Keyword(s):  
High Throughput ◽  
Fir Filter ◽  
Data Streaming ◽  
Low Area ◽  
Dsp Applications

scholarly journals Multi-Level Elasticity for Wide-Area Data Streaming Systems: A Reinforcement Learning Approach

Algorithms ◽  
2018 ◽  
Vol 11 (9) ◽  
pp. 134 ◽  
Author(s):  
Gabriele Russo Russo ◽  
Matteo Nardelli ◽  
Valeria Cardellini ◽  
Francesco Lo Presti
Keyword(s):  
Reinforcement Learning ◽  
High Volume ◽  
Wide Area ◽  
Data Streaming ◽  
Application Performance ◽  
Ubiquitous Sensing ◽  
Self Adaptation ◽  
Adaptation Policies ◽  
Multi Level ◽  
Dsp Applications

The capability of efficiently processing the data streams emitted by nowadays ubiquitous sensing devices enables the development of new intelligent services. Data Stream Processing (DSP) applications allow for processing huge volumes of data in near real-time. To keep up with the high volume and velocity of data, these applications can elastically scale their execution on multiple computing resources to process the incoming data flow in parallel. Being that data sources and consumers are usually located at the network edges, nowadays the presence of geo-distributed computing resources represents an attractive environment for DSP. However, controlling the applications and the processing infrastructure in such wide-area environments represents a significant challenge. In this paper, we present a hierarchical solution for the autonomous control of elastic DSP applications and infrastructures. It consists of a two-layered hierarchical solution, where centralized components coordinate subordinated distributed managers, which, in turn, locally control the elastic adaptation of the application components and deployment regions. Exploiting this framework, we design several self-adaptation policies, including reinforcement learning based solutions. We show the benefits of the presented self-adaptation policies with respect to static provisioning solutions, and discuss the strengths of reinforcement learning based approaches, which learn from experience how to optimize the application performance and resource allocation.

Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing

2020 ◽  
Vol 29 (14) ◽  
pp. 2050233
Author(s):  
Zhixi Yang ◽  
Xianbin Li ◽  
Jun Yang
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal Processing ◽  
Resource Utilization ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Electrical Performance ◽  
Approximate Computing ◽  
Dsp Applications

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

High-throughput low-area design of AES using constant binary matrix-vector multiplication

2016 ◽  
Vol 47 ◽  
pp. 360-368 ◽  
Author(s):  
Hokyoon Lee ◽  
Yoonah Paik ◽  
Jaeyung Jun ◽  
Youngsun Han ◽  
Seon Wook Kim
Keyword(s):  
High Throughput ◽  
Binary Matrix ◽  
Low Area ◽  
Matrix Vector Multiplication ◽  
Matrix Vector

scholarly journals High-Throughput Low-Area Hardware Design of Authenticated Encryption with Associated Data Cryptosystem that Uses ChaCha20 and Poly1305

2019 ◽  
Vol 8 (2S6) ◽  
pp. 86-94
Keyword(s):  
High Throughput ◽  
Stream Cipher ◽  
Hardware Design ◽  
Authenticated Encryption ◽  
Verilog Hdl ◽  
Low Area ◽  
Cell Library ◽  
Wide Range ◽  
Exclusive Or ◽  
Associated Data

In this paper, the hardware design of a low area and a high throughput ChaCha20-Poly1305 that performs the dual authentication-encryption function for a secured communication within hardware devices is presented. Cryptographic algorithms- ChaCha20 stream cipher and Poly1305, enhance security margins and achieve higher performance measures on a wide range of software platforms and has proven superior to its counterpart, the AES, in the software domain. This relatively new stream cipher is compared to the benchmark AES, has recently been standardized but their implementations in hardware have had very little to not very desirable results particularly in terms of area. For this reason, it is therefore an active field to make such algorithms hardware friendly. This research presents a compact, low-area and high throughput chacha20-Poly1305 Authenticated Encryption with Associated Data (AEAD) design. The core architecture consists of the ChaCha20-Poly1305 algorithm. The simplified quarter round designed in the proposed architecture uses the addition, rotation and exclusive-or algorithms operators (gates). This proposed architecture provides an improvement in the operating frequency and area. The architecture was modeled and simulated with Verilog HDL and Modelsim tools for functional and timing correctness. The hardware architecture designed was synthesized with Xilinx‟s Synthesis Tool (XST) and Synopsis‟ Design Compiler (DC) using the 0.18µm CMOS standard Cell library. The resulting hardware area in terms of gate equivalent is approximately 11KGE for chacha20 and 21KGE for Poly1305. The design operates at maximum frequency of 420 MHz and 870 MHz for the ChaCha20 and Poly1305 respectively. The proposed design presented in this paper additionally functions at a throughput of approximately 8 Gbps for ChaCha20 with an overall efficiency of 2.35 Kbps/GE when ChaCha20 and Poly1305 are combined into the AEAD_ChaCha20_Poly1305 authenticated encryption core.

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