High performance hardware architectures for the inverse Rotational Transform of the emerging HEVC standard

Author(s):  
Henrique Vianna ◽  
Gustavo Sanchez ◽  
Marcelo Porto ◽  
Luciano Agostini
2010 ◽  
Vol Special Issue (1) ◽  
pp. 71-79 ◽  
Author(s):  
Marek Błażewicz ◽  
Krzysztof Kurowski ◽  
Bogdan Ludwiczak ◽  
Krystyna Napierała

2019 ◽  
Vol 85 (6) ◽  
Author(s):  
Alessandro Zocco ◽  
Alexey Mishchenko ◽  
Axel Könies

We show analytically that for $\unicode[STIX]{x1D704}$ -profiles similar to the one of the Wendelstein 7-X stellarator, where $\unicode[STIX]{x1D704}$ is the rotational transform of the equilibrium magnetic field, a highly conducting toroidal plasma is unstable to kinetically mediated pressure-driven long-wavelength reconnecting modes, of the infernal type. The modes are destabilized either by the electron temperature gradient or by a small amount of current, depending on how far from unity the average value of $\unicode[STIX]{x1D704}$ is, which is assumed to be slowly varying. We argue that, for W7-X, a broad mode with toroidal and poloidal mode numbers $(n,m)=(1,1)$ can be destabilized due to the strong geometric side-band coupling of the resonant kinetic electron response at locations where $\unicode[STIX]{x1D704}$ is rational for harmonics that belong to the mode family of the $(n,m)=(1,1)$ mode itself. In many regimes, the growth rate is insensitive to the plasma density, thus it is likely to persist in high performance W7-X discharges. For a peaked electron temperature, with a maximum of $T_{e}=5~\text{keV}$ , larger than the ion temperature, $T_{i}=2.5~\text{keV}$ , and a density $n_{0}=10^{19}~\text{m}^{-3}$ , instability is found in regimes which show plasma sawtooth activity, with growth rates of the order of tens of kiloHertz. Frequencies are either electron diamagnetic or of the ideal magnetohydrodynamic type, but sub-Alfvénic. The kinetic infernal mode is thus a good candidate for the explanation of sawtooth oscillations in present-day stellarators and poses a new challenge to the problem of stellarator reactor optimization.


2015 ◽  
Vol 26 (4) ◽  
pp. 18-43 ◽  
Author(s):  
Markus Endres ◽  
Werner Kießling

The problem of Skyline computation has attracted considerable research attention in the last decade. A Skyline query selects those tuples from a dataset that are optimal with respect to a set of designated preference attributes. Since multicore processors are going mainstream, it has become imperative to develop parallel algorithms, which fully exploit the advantages of such modern hardware architectures. In this paper, the authors present high-performance parallel Skyline algorithms based on the lattice structure generated by a Skyline query. For this, they propose different evaluation strategies and compare several data structures for the parallel evaluation of Skyline queries. The authors present novel optimization techniques for lattice based Skyline algorithms based on pruning and removing one unrestricted attribute domain. They demonstrate through comprehensive experiments on synthetic and real datasets that their new algorithms outperform state-of-the-art multicore Skyline techniques for low-cardinality domains. The authors' algorithms have linear runtime complexity and fully play on modern hardware architectures.


2016 ◽  
Vol 25 (08) ◽  
pp. 1650083
Author(s):  
P. Muralidhar ◽  
C. B. Rama Rao

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133[Formula: see text]MHz and is capable of processing full high definition (HD) ([Formula: see text]) frames at a rate of 60 frames per second.


2020 ◽  
Vol 12 (7) ◽  
pp. 113 ◽  
Author(s):  
Maurizio Capra ◽  
Beatrice Bussolino ◽  
Alberto Marchisio ◽  
Muhammad Shafique ◽  
Guido Masera ◽  
...  

Deep Neural Networks (DNNs) are nowadays a common practice in most of the Artificial Intelligence (AI) applications. Their ability to go beyond human precision has made these networks a milestone in the history of AI. However, while on the one hand they present cutting edge performance, on the other hand they require enormous computing power. For this reason, numerous optimization techniques at the hardware and software level, and specialized architectures, have been developed to process these models with high performance and power/energy efficiency without affecting their accuracy. In the past, multiple surveys have been reported to provide an overview of different architectures and optimization techniques for efficient execution of Deep Learning (DL) algorithms. This work aims at providing an up-to-date survey, especially covering the prominent works from the last 3 years of the hardware architectures research for DNNs. In this paper, the reader will first understand what a hardware accelerator is, and what are its main components, followed by the latest techniques in the field of dataflow, reconfigurability, variable bit-width, and sparsity.


Author(s):  
Domen Verber

A state-of-the-art and a possible future of High Performance Computing (HPC) are discussed. The steady advances in hardware have resulted in increasingly more powerful computers. Some HPC applications that were years ago only in the domain of supercomputers can nowadays be executed on desktop and mobile computers. Furthermore, the future of computers is in the “Internet-of-things” and cyber-physical systems. There, computers are embedded into the devices such as cars, house appliances, production lines, into our clothing, etc. They are interconnected with each other and they may cooperate. Based on that, a new kind of application emerges, which requires the HPC architectures and development techniques. The primary focus of the chapter is on different hardware architectures for HPC and some particularities of HPC programming. Some alternatives to traditional computational models are given. At the end, some replacements for semiconductor technologies of modern computers are debated.


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