scholarly journals High Performance SDN Hardware Architectures and Their Uses in the Evolving Transport Network

2017 ◽  
Author(s):  
Yatish Kumar
Keyword(s):  
High Performance ◽  
Transport Network ◽  
Hardware Architectures

scholarly journals High Performance Computing on New Accelerated Hardware Architectures

2010 ◽  
Vol Special Issue (1) ◽  
pp. 71-79 ◽  
Author(s):  
Marek Błażewicz ◽  
Krzysztof Kurowski ◽  
Bogdan Ludwiczak ◽  
Krystyna Napierała
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
Hardware Architectures ◽  
Performance Computing

Parallel Skyline Computation Exploiting the Lattice Structure

2015 ◽  
Vol 26 (4) ◽  
pp. 18-43 ◽  
Author(s):  
Markus Endres ◽  
Werner Kießling
Keyword(s):  
High Performance ◽  
Lattice Structure ◽  
Multicore Processors ◽  
Optimization Techniques ◽  
Skyline Query ◽  
Research Attention ◽  
Evaluation Strategies ◽  
Hardware Architectures ◽  
Parallel Evaluation ◽  
New Algorithms

The problem of Skyline computation has attracted considerable research attention in the last decade. A Skyline query selects those tuples from a dataset that are optimal with respect to a set of designated preference attributes. Since multicore processors are going mainstream, it has become imperative to develop parallel algorithms, which fully exploit the advantages of such modern hardware architectures. In this paper, the authors present high-performance parallel Skyline algorithms based on the lattice structure generated by a Skyline query. For this, they propose different evaluation strategies and compare several data structures for the parallel evaluation of Skyline queries. The authors present novel optimization techniques for lattice based Skyline algorithms based on pruning and removing one unrestricted attribute domain. They demonstrate through comprehensive experiments on synthetic and real datasets that their new algorithms outperform state-of-the-art multicore Skyline techniques for low-cardinality domains. The authors' algorithms have linear runtime complexity and fully play on modern hardware architectures.

High Performance Architecture of Motion Estimation Algorithm for Video Compression

2016 ◽  
Vol 25 (08) ◽  
pp. 1650083
Author(s):  
P. Muralidhar ◽  
C. B. Rama Rao
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Estimation Algorithm ◽  
Block Matching ◽  
High Definition ◽  
Systolic Architecture ◽  
Hardware Architectures ◽  
Computationally Intensive ◽  
Full Search

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133[Formula: see text]MHz and is capable of processing full high definition (HD) ([Formula: see text]) frames at a rate of 60 frames per second.

scholarly journals Pronlem of Selecting Communication Channels Bandwidth of Transport Network Taking into Account imbalance of Various Priority Traffic

2020 ◽  
Vol 19 (2) ◽  
pp. 412-445 ◽  
Author(s):  
Sergej Andreev ◽  
Roman Tregubov ◽  
Alexander Mironov
Keyword(s):  
Communication Network ◽  
Quality Of Service ◽  
Lagrange Multipliers ◽  
High Performance ◽  
Digital Communication ◽  
Communication Channels ◽  
Transport Network ◽  
Network Simulator ◽  
Optimal Bandwidth

The paper proposes a solution to the problem of selecting the bandwidth capabilities of digital communication channels of a transport communication network taking into account the imbalance of data traffic by priorities. The algorithm for selecting bandwidth guarantees the minimum costs associated with renting digital communication channels with optimal bandwidth, provided that the requirements for quality of service of protocol data blocks of the first, second, and k-th priority in an unbalanced in terms of priorities transport communication network are met. At the first stage of solving the problem, using the method of Lagrange multipliers, an algorithm for selecting the capacities of digital communication channels for a balanced in terms of priorities transport network was developed. High performance of this algorithm was ensured by applying algebraic operations on matrices (addition, multiplication, etc.). At the second stage of solving the problem, using the generalized Lagrange multipliers method, we compared the conditional extrema of the cost function for renting digital communication channels for single active quality of service requirements for protocol data blocks, for all possible pairs of active quality of service requirements for protocol data blocks, for all possible triples of active requirements for the quality of service of protocol data units, and so on up to the case when all the requirements for quality of service maintenance of protocol data units are active simultaniously. At the third stage of solving the problem, an example of selecting the bandwidth capabilities of digital communication channels of the unbalanced by priorities transport network consisting of eight routers serving protocol data blocks of three priorities was considered. At the fourth stage of the solution of the problem of the choice of carrying capacities the estimation of efficiency of the developed algorithm by a method of simulation modeling was carried out. To this end, in the environment of the network simulator OMNet ++, the unbalanced in terms of priority transport communication network consisting of eight routers connected by twelve digital communication channels with optimal bandwidth was investigated.

A high-performance transport network platform

1995 ◽  
Vol 34 (4) ◽  
pp. 705-724 ◽  
Author(s):  
G. Lebizay ◽  
C. Galand ◽  
D. Chevalier ◽  
F. Barre
Keyword(s):  
High Performance ◽  
Transport Network ◽  
Network Platform

scholarly journals An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks

2020 ◽  
Vol 12 (7) ◽  
pp. 113 ◽  
Author(s):  
Maurizio Capra ◽  
Beatrice Bussolino ◽  
Alberto Marchisio ◽  
Muhammad Shafique ◽  
Guido Masera ◽  
...  
Keyword(s):  
Neural Networks ◽  
High Performance ◽  
Optimization Techniques ◽  
Deep Convolutional Neural Networks ◽  
Computing Power ◽  
The Past ◽  
History Of ◽  
Hardware Architectures ◽  
The One ◽  
Main Components

Deep Neural Networks (DNNs) are nowadays a common practice in most of the Artificial Intelligence (AI) applications. Their ability to go beyond human precision has made these networks a milestone in the history of AI. However, while on the one hand they present cutting edge performance, on the other hand they require enormous computing power. For this reason, numerous optimization techniques at the hardware and software level, and specialized architectures, have been developed to process these models with high performance and power/energy efficiency without affecting their accuracy. In the past, multiple surveys have been reported to provide an overview of different architectures and optimization techniques for efficient execution of Deep Learning (DL) algorithms. This work aims at providing an up-to-date survey, especially covering the prominent works from the last 3 years of the hardware architectures research for DNNs. In this paper, the reader will first understand what a hardware accelerator is, and what are its main components, followed by the latest techniques in the field of dataflow, reconfigurability, variable bit-width, and sparsity.

The Future of Supercomputers and High-Performance Computing

2015 ◽  
pp. 152-164
Author(s):  
Domen Verber
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
Computational Models ◽  
Production Lines ◽  
The Future ◽  
Hardware Architectures ◽  
Primary Focus ◽  
Mobile Computers ◽  
Performance Computing ◽  
The Internet Of Things

A state-of-the-art and a possible future of High Performance Computing (HPC) are discussed. The steady advances in hardware have resulted in increasingly more powerful computers. Some HPC applications that were years ago only in the domain of supercomputers can nowadays be executed on desktop and mobile computers. Furthermore, the future of computers is in the “Internet-of-things” and cyber-physical systems. There, computers are embedded into the devices such as cars, house appliances, production lines, into our clothing, etc. They are interconnected with each other and they may cooperate. Based on that, a new kind of application emerges, which requires the HPC architectures and development techniques. The primary focus of the chapter is on different hardware architectures for HPC and some particularities of HPC programming. Some alternatives to traditional computational models are given. At the end, some replacements for semiconductor technologies of modern computers are debated.

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