A Survey on System-on-a-Chip Design Using Chisel HW Construction Language

2021 ◽  
Author(s):  
Matti Kayra ◽  
Timo D. Hamalainen
Keyword(s):  
Chip Design ◽  
System On A Chip

scholarly journals Coopetition in the SoC Industry: The Case of Qualcomm Incorporated

2020 ◽  
Vol 6 (1) ◽  
pp. 9
Author(s):  
Yona Kwon ◽  
Dahee Kang ◽  
Sinji Kim ◽  
Seungho Choi
Keyword(s):  
Global Positioning System ◽  
Case Analysis ◽  
Competitive Dynamics ◽  
Smart Devices ◽  
Positioning System ◽  
Chip Design ◽  
Cooperation And Competition ◽  
Global Positioning ◽  
System On A Chip

This study uses the lens of competitive dynamics to examine the coopetition process, which combines both cooperation and competition, employed by Qualcomm within the SoC (System on a Chip) design market related to smart devices. Qualcomm succeeded in developing the first SoC, which integrated GPS (Global Positioning System) and other software, and during the process of developing mobile chips has simultaneously cooperated and competed with competitors. In particular, Samsung, which began as a customer of the firm, has since become its competitor. By conducting descriptive case analysis, this study shows a coopetition process in the SoC industry and supplemented a coopetition study with the actual exemplary coopetition case.

scholarly journals Giga-Scale Integration System-On-A-Chip Design: Challenges and Noteworthy Solutions

2020 ◽  
Vol 8 (6) ◽  
pp. 741-746
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Chip Design ◽  
Future Challenges ◽  
System On A Chip ◽  
And Performance ◽  
Exponential Rates ◽  
Scale Integration ◽  
Bus Architecture ◽  
Circuit Technology

In all respects of the last five decades, integrated circuit technology has advanced at exponential rates in both productivity and performance. Giga-Scale Integration (GSI) System-On-A-Chip (SoC) designs have become one of the main drivers of the integrated circuit technology in recent years. The objective of this work is to understand the challenges of Giga-scale SoC integration in nanometer technologies, and identify promising conveniences for innovation. Physical designs are crucial for SoC integration and in our work we identify them with details. In future the couplings and interactions among system components will increase as we put more of the system on a silicon die. Therefore the system designers will face challenges in several areas and we describe these future challenges briefly. Developing a design driver for GSI SoC design is important. With the help of this design driver we provide the design methodology, which ensures the high performance of the design. We present two noteworthy solutions which overcome the challenges of GSI SoC design. One is reuse and integration and another is efficient bus architecture. We also provide the challenges for verification of GSI SoC and methods to overcome these challenges.

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