scholarly journals Giga-Scale Integration System-On-A-Chip Design: Challenges and Noteworthy Solutions

2020 ◽  
Vol 8 (6) ◽  
pp. 741-746
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Chip Design ◽  
Future Challenges ◽  
System On A Chip ◽  
And Performance ◽  
Exponential Rates ◽  
Scale Integration ◽  
Bus Architecture ◽  
Circuit Technology

In all respects of the last five decades, integrated circuit technology has advanced at exponential rates in both productivity and performance. Giga-Scale Integration (GSI) System-On-A-Chip (SoC) designs have become one of the main drivers of the integrated circuit technology in recent years. The objective of this work is to understand the challenges of Giga-scale SoC integration in nanometer technologies, and identify promising conveniences for innovation. Physical designs are crucial for SoC integration and in our work we identify them with details. In future the couplings and interactions among system components will increase as we put more of the system on a silicon die. Therefore the system designers will face challenges in several areas and we describe these future challenges briefly. Developing a design driver for GSI SoC design is important. With the help of this design driver we provide the design methodology, which ensures the high performance of the design. We present two noteworthy solutions which overcome the challenges of GSI SoC design. One is reuse and integration and another is efficient bus architecture. We also provide the challenges for verification of GSI SoC and methods to overcome these challenges.

scholarly journals The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

2004 ◽  
Vol 17 (3) ◽  
pp. 285-312
Author(s):  
Mile Stojcev ◽  
Teufik Tokic ◽  
Ivan Milentijevic
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
New Technology ◽  
Process Technology ◽  
History Of ◽  
And Performance ◽  
Thread Level Speculation ◽  
Exponential Rates ◽  
Architecture And Design ◽  
Integrated Circuit Industry

In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance. The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide. The technology that enabled this exponential growth is a combination of advancements in process technology, micro architecture architecture and design and development tools. Together, these performances and functionality improvements have resulted in a history of new technology generations every two to three years, commonly referred to as-Moore Law. Each new generation has approximately doubled logic circuit density and increased performance by about 40%. This paper overviews some of the micro architectural techniques that are typical for contemporary high-performance microprocessors. The techniques are classified into those that increase the concurrency in instruction processing, while maintaining the appearance of sequential processing (pipelining, super-scalar execution out-of-order execution, etc), and those that exploit program behavior (memories hierarchies, branch predictors, trace caches, etc). In addition the paper also discusses micro architectural techniques likely to be used in the near future such as micro architectures with multiple sequencers and thread-level speculation, and micro architectural techniques intended for minimization of power consumption.

PERFORMANCE AT THE EDGE: GALLIUM ARSENIDE AND SILICON ICs FOR OPTICAL ELECTRONICS

1991 ◽  
Vol 02 (03) ◽  
pp. 147-162 ◽  
Author(s):  
ROBERT G. SWARTZ
Keyword(s):  
Gallium Arsenide ◽  
Optical Communication ◽  
Optical Communications ◽  
Integrated Circuit ◽  
High Performance ◽  
Compound Semiconductor ◽  
Performance Curve ◽  
Semiconductor Technology ◽  
Market Trends ◽  
Circuit Technology

Compound semiconductor technology is rapidly entering the mainstream, and is quickly finding its way into consumer applications where high performance is paramount. But silicon integrated circuit technology is evolving up the performance curve, and CMOS in particular is consuming ever more market share. Nowhere is this contest more clearly evident than in optical communications. Here applications demand performance ranging from a few hundreds of megahertz to multi-gigahertz, from circuits containing anywhere from tens to tens of thousands of devices. This paper reviews the high performance electronics found in optical communication applications from a technology standpoint, illustrating merits and market trends for these competing, yet often complementary IC technologies.

scholarly journals Special Issue on Intelligent Integrated Systems for Robotics

1994 ◽  
Vol 6 (2) ◽  
pp. 119-119
Author(s):  
Michitaka Kameyama ◽  
Keyword(s):  
Real World ◽  
Integrated Circuit ◽  
Integrated Systems ◽  
Next Generation ◽  
Special Issue ◽  
Robot Systems ◽  
Scale Integration ◽  
Near Future ◽  
Circuit Technology

The new area of ""intelligent integrated systems"" has been proposed to develop one of the generic technologies for next-generation electronics and information systems. Although the interpretation may be different for individual persons, I think the area is the integration of the three concepts as shown in Figure. One is the concept of ""system on silicon"" using the integrated circuit technology. Giga-scale integration will be available in near future, so that we have to develop hardware and software architecture related to ultra highly parallel processing. Another is the concept of intelligence including physical model based computations as well as AI technology. The other is the concept of real-world applications just different from computer-world applications. The signal flow is passed through a real world, so that the performance should be evaluated as the response time or delay time. The examples are robotics, car electronics, home electronics, factory automation and so on. This special issue is planned to demonstrate the above important area, especially dedicated for robotics which is a typical example of the intelligent integrated systems. I believe that the contents of this issue give great impact on' the next-generation robot systems, and it will be a memorial publication. Finally, I would like to express my appreciation to the authors for their efforts and contributions to this special issue and also to the members of the Editorial Board for their useful comments.

An Approach to Reading Machine Design

1978 ◽  
Vol 20 (3) ◽  
pp. 287-293 ◽  
Author(s):  
Jonathan Allen
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Read Aloud ◽  
Machine Design ◽  
Current Status ◽  
Text To Speech ◽  
Short Term ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Circuit Technology

Within two years, both the required algorithmic competence and the necessary integrated circuit technology will have been developed to a point where practical personal reading machines for the blind will be possible. In this paper, the linguistic and phonetic principles needed to convert optically recognized text to speech are discussed, and it is shown how they mirror the human cognitive ability to read aloud. A perspective on the current status and rate of progress of large scale integration technology is then used to show that economical implementations of even complex text-to-speech algorithms can be realized in the short-term future. Finally, a view of important human factors problems requiring attention is given.

Process Design & Integration of Salicide and Source/Drain Process Modules for Improved Device Performance

1998 ◽  
Vol 525 ◽  
Author(s):  
Pushkar P. Apte ◽  
Sharad Saxena ◽  
Suraj Rao ◽  
Karthik Vasanth ◽  
Douglas A. Prinslow ◽  
...  
Keyword(s):  
Process Design ◽  
Integrated Circuit ◽  
High Performance ◽  
Performance Enhancement ◽  
Process Integration ◽  
Channel Length ◽  
Trade Offs ◽  
Design Integration ◽  
And Performance ◽  
Circuit Delays

ABSTRACTIn integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (Id) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as Rc vs Rs and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

Design of SoC Verification System Based on Multi-FPGA

2012 ◽  
Vol 532-533 ◽  
pp. 1110-1114
Author(s):  
Xi Han ◽  
Zhe Ying Li ◽  
Yuan Sheng Liu ◽  
Wen Liang Niu
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
Technical Problem ◽  
Initial Step ◽  
Research Field ◽  
Chip Design ◽  
Fpga Verification ◽  
Field Programmable ◽  
Fpga Chip ◽  
System On A Chip

As one of the most advanced research field, the problem of SoC (System on a Chip) design is getting more and more attention. With the promotion of its theory and technique, SoC verification turns to one of the most significant part in the procedure of realizing a usable integrated circuit. And verification using FPGA (Field Programmable Gate Array) which must obey a set of strict technological process is a kind of general way. With the growing complexity and integrated scale of SoC design, a single FPGA chip could hardly satisfy the verification requirement. Then the method of verification using multi-FPGA is taken and expresses some advantages in some respects. Multi-FPGA verification is still in the initial step situation and has a broad developing space. The architecture of multi-FPGA verification platform is given in this paper, as well as some related key technical problem and solutions.

scholarly journals An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

2012 ◽  
Vol 2012 ◽  
pp. 1-15 ◽  
Author(s):  
Andrew G. Schmidt ◽  
William V. Kritikos ◽  
Shanyuan Gao ◽  
Ron Sass
Keyword(s):  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
Large Scale ◽  
The Body ◽  
And Performance ◽  
On Chip ◽  
Point To Point ◽  
Computing Machines ◽  
Performance Computing

As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster. The system supports MPI-style point-to-point messages, collectives, and other novel communication. Results include the resource utilization and performance (in latency and bandwidth).

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

Trace nanoanalysis

1994 ◽  
Vol 52 ◽  
pp. 940-941
Author(s):  
D. E. Newbury ◽  
R. D. Leapman
Keyword(s):  
High Performance ◽  
Secondary Ion Mass Spectrometry ◽  
Detection Efficiency ◽  
Volume Element ◽  
And Performance ◽  
Trace Constituents ◽  
Secondary Ion ◽  
Concentration Levels ◽  
Structure Properties

Trace constituents, which can be very loosely defined as those present at concentration levels below 1 percent, often exert influence on structure, properties, and performance far greater than what might be estimated from their proportion alone. Defining the role of trace constituents in the microstructure, or indeed even determining their location, makes great demands on the available array of microanalytical tools. These demands become increasingly more challenging as the dimensions of the volume element to be probed become smaller. For example, a cubic volume element of silicon with an edge dimension of 1 micrometer contains approximately 5×1010 atoms. High performance secondary ion mass spectrometry (SIMS) can be used to measure trace constituents to levels of hundreds of parts per billion from such a volume element (e. g., detection of at least 100 atoms to give 10% reproducibility with an overall detection efficiency of 1%, considering ionization, transmission, and counting).

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