Self-Synchronization Scheme for Network of Grid-following and Grid-forming Photovoltaic Inverters

Author(s):  
Shantanu Gupta ◽  
Muhammad F. Umar ◽  
Mohammad B. Shadmand ◽  
Sudip K. Mazumder
2013 ◽  
Vol 333-335 ◽  
pp. 472-479
Author(s):  
Jian Fei An ◽  
Ke Zhu Song ◽  
Lin Feng Shang ◽  
Jun Feng Yang

In land seismic data acquisition systems, as seismic exploration goes towards to cover large area, a multi-channel structure is needed. In such systems, synchronization is very important, which has great influence on data acquisition and transmission. In this paper, a clock synchronization scheme for seismic exploration is proposed. In the scheme, LVDS serial transmission is used so that the whole system clocks can be made to have the same frequency through clock data recovery technique. Moreover, to compensate the effect caused by transmission delay, an effective algorithm based on PLL phase locked and FPGA logic is proposed in this scheme. The test results show that this scheme meets the system clock synchronization requirements well with the error precision less than 1ns, which fully demonstrates the feasibility and reliability of the scheme. The scheme proposed here can be used in related systems which require clock synchronization.


2006 ◽  
Vol 16 (10) ◽  
pp. 3087-3091 ◽  
Author(s):  
YONG HE ◽  
GUILIN WEN ◽  
QING-GUO WANG

A master-slave synchronization scheme for Lur'e systems is studied for a known delay existing between master and slave systems. Based on the latest development of stability studies for time-delay systems, a new delay-dependent synchronization criterion is derived by the free-weighting matrix approach. The criterion shown by example is less conservative than the existing synchronization criteria.


2021 ◽  
Vol 26 (3-4) ◽  
pp. 282-290
Author(s):  
S.V. Volobuev ◽  
◽  
V.G. Ryabtsev ◽  

The I/О synchronization scheme plays an important role in achieving maximum speed and reliability of data transmission during memory operation. This paper presents the interface architecture of the DDR SDRAM test diagnostic device. It was demonstrated that the proposed interface components provide the formation of a bidirectional synchro signal for gating written and read data when performing test diagnostics of chips and DDR SDRAM memory devices. Compared to traditional methods, the proposed interface components were made on integrated electronic elements, which reduced the size and power consumption. It has been established that the use of a multiphase synchronization system to implement the interface eliminated the use of delay lines, the disadvantages of which are large dimensions and the complexity of changing the delay time. The interface components under consideration are intended for use in test diagnostics devices that have a multiprocessor structure, which increases the speed of forming test actions and reference reactions. The performed functional modeling and debugging of strobe signal generators confirmed the feasibility of the designs. The proposed interface of the test diagnostics device allows performing test diagnostics of modern high-speed chips and semiconductor memory modules at the operating frequency, which increases the reliability of the results obtained. Interface components can be used by manufacturers of test diagnostics tools for modern high-speed storage devices.


Author(s):  
Kevin H. M. Gularte ◽  
Juan C. G. Gomez ◽  
Jose A. R. Vargas ◽  
Rogerio R. Dos Santos

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