Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

Author(s):  
R. Ritzenthaler ◽  
H. Mertens ◽  
V. Pena ◽  
G. Santoro ◽  
A. Chasin ◽  
...  
2002 ◽  
Vol 23 (4) ◽  
pp. 200-202 ◽  
Author(s):  
I. Polishchuk ◽  
P. Ranade ◽  
T.-J. King ◽  
Chenming Hu

2007 ◽  
Vol 28 (12) ◽  
pp. 1089-1091 ◽  
Author(s):  
R. Singanamalla ◽  
H. Y. Yu ◽  
B. Van Daele ◽  
S. Kubicek ◽  
K. De Meyer

2013 ◽  
Vol 88 ◽  
pp. 21-26 ◽  
Author(s):  
C. Leroux ◽  
S. Baudot ◽  
M. Charbonnier ◽  
A. Van Der Geest ◽  
P. Caubet ◽  
...  

2007 ◽  
Vol 91 (9) ◽  
pp. 092106 ◽  
Author(s):  
H. R. Gong ◽  
Kyeongjae Cho

2011 ◽  
Vol 2 (1) ◽  
pp. 11-24 ◽  
Author(s):  
Deepesh Ranka ◽  
Ashwani K. Rana ◽  
Rakesh Kumar Yadav ◽  
Kamalesh Yadav ◽  
Devendra Giri

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