Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the many
DFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paper
we explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flops
and obtain reasonably high coverage. This approach has lower overhead in terms of test application time
and hardware area when compared to previous ones. Further enhancement of the controllability is obtained by
using multiple reset lines. The configuration of these multiple reset lines is described. This technique has been
evaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.
A Hybrid Test Architecture to Reduce Test Application Time in Full Scan Sequential Circuits
