scholarly journals Partial Reset: An Alternative DFT Approach

VLSI Design ◽  
1994 ◽  
Vol 1 (4) ◽  
pp. 299-311 ◽  
Author(s):  
Ben Mathew ◽  
Daniel G. Saab
Keyword(s):  
Dft Method ◽  
Design For Testability ◽  
Application Time ◽  
High Coverage ◽  
Partial Scan ◽  
Test Application Time ◽  
Test Application ◽  
Full Scan ◽  
The Many ◽  
Partial Reset

Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the many DFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paper we explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flops and obtain reasonably high coverage. This approach has lower overhead in terms of test application time and hardware area when compared to previous ones. Further enhancement of the controllability is obtained by using multiple reset lines. The configuration of these multiple reset lines is described. This technique has been evaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.

A Hybrid Delay Design-for-Testability for Nonseparable RTL Controller-Data Path Circuits

2016 ◽  
Vol 26 (02) ◽  
pp. 1750021
Author(s):  
Ateeq-Ur-Rehman Shaheen ◽  
Fawnizu Azmadi Hussin ◽  
Nor Hisham Hamid
Keyword(s):  
Dft Method ◽  
Data Path ◽  
Path Delay ◽  
Application Time ◽  
Large Area ◽  
Process Technology ◽  
Test Application Time ◽  
Area Overhead ◽  
Test Application ◽  
Pdf Model

Path delay testing has become crucial nowadays due to the advancement in process technology. Only enhanced scan (ES) among the scan approaches provides a solution to test the path delay fault (PDF) with large area overhead and the long test application time. This paper proposes a hybrid DFT method for nonseparable controller-data path RTL circuits. A snooping system is introduced which reduces the test application time. It performs the PDF testing between the controller and data path, and for the not-Clear control lines in the data path. The proposed method shared primary inputs and outputs to overcome the extra pin. However, the area overhead for the proposed approach is slightly large for the circuit with a small bit-width data path, which reduced drastically by the increase in the bit-width. The proposed approach supports the at-speed testing and is based on the PDF model. The experimental results showed that the proposed approach reduces the area overhead and drastically reduces the test application time in comparison with the enhanced scan (ES) and hierarchical two-pattern testability (HTPT) approach. Moreover, the technique can achieve a fault coverage identical to that achieved by the ES technique.

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