Power efficient design of a novel SRAM cell with higher write ability

2015 ◽  
Author(s):  
Debasish Nayak ◽  
D.P. Acharya ◽  
K.K. Mahapatra
Keyword(s):  
Efficient Design ◽  
Power Efficient ◽  
Sram Cell

A power-efficient impoved-stability 6T SRAM cell in 45nm Multi-Channel FET technology

2008 ◽  
Author(s):  
Olivier Thomas ◽  
Bernard Guillaumot ◽  
Thomas Ernst ◽  
Bastien Cousin ◽  
Olivier Rozeau
Keyword(s):  
Power Efficient ◽  
Sram Cell

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

Outage Constrained Power Efficient Design for Downlink NOMA Systems With Partial HARQ

2020 ◽  
Vol 68 (8) ◽  
pp. 5188-5201 ◽  
Author(s):  
Yanqing Xu ◽  
Donghong Cai ◽  
Fang Fang ◽  
Zhiguo Ding ◽  
Chao Shen ◽  
...  
Keyword(s):  
Efficient Design ◽  
Power Efficient

scholarly journals Power-conscious Scheduling for Real-time Embedded Systems Design

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 139-150 ◽  
Author(s):  
Youngsoo Shin ◽  
Kiyoung Choi ◽  
Takayasu Sakurai
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Systems Design ◽  
Optimization Method ◽  
Efficient Design ◽  
Power Efficient ◽  
On Line ◽  
Time Variations ◽  
Processor Speed ◽  
Programmable Processors

Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. We address a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode to exploit execution time variations and idle intervals. Experimental results show that the proposed method obtains a significant power reduction across several kinds of applications.

scholarly journals Efficient Design of Control Logic Block in Dual Port Memory

2020 ◽  
Vol 8 (6) ◽  
pp. 841-845
Keyword(s):  
Efficient Design ◽  
Memory Location ◽  
Control Logic ◽  
Lower Priority ◽  
Read Operation ◽  
Logic Block ◽  
Sram Cell ◽  
A Priority ◽  
Data Priority

A dual port memory in QCA are a study of data in different ports, but the data conflicts are very difficult to identify. Dual port memory is mainly focused on the data priority. It can be generated from the design of the control logic block. Priority bit are used, where both ports access the same memory location. Dual port memory functionality can be identified with a priority bit. When the port having the same memory location, only the port having the high priority is selected and other port are discarded. But when the read operation are requested to both the ports at same locations, having no conflicts and both the ports are requested to perform read operations. Data conflicts on the SRAM cell can be overcome by discarding the lower priority completely. Priorities are defined in terms of the area and delay. The idea behind this work is to minimize the area and delay in the dual port memory and proposed a multilayer Cross-Over design to provide an efficiency to the dual port memory and simulation result of design are shown in QCA Designer Tool-2.0.

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