scholarly journals Efficient Design of Control Logic Block in Dual Port Memory

2020 ◽  
Vol 8 (6) ◽  
pp. 841-845
Keyword(s):  
Efficient Design ◽  
Memory Location ◽  
Control Logic ◽  
Lower Priority ◽  
Read Operation ◽  
Logic Block ◽  
Sram Cell ◽  
A Priority ◽  
Data Priority

A dual port memory in QCA are a study of data in different ports, but the data conflicts are very difficult to identify. Dual port memory is mainly focused on the data priority. It can be generated from the design of the control logic block. Priority bit are used, where both ports access the same memory location. Dual port memory functionality can be identified with a priority bit. When the port having the same memory location, only the port having the high priority is selected and other port are discarded. But when the read operation are requested to both the ports at same locations, having no conflicts and both the ports are requested to perform read operations. Data conflicts on the SRAM cell can be overcome by discarding the lower priority completely. Priorities are defined in terms of the area and delay. The idea behind this work is to minimize the area and delay in the dual port memory and proposed a multilayer Cross-Over design to provide an efficiency to the dual port memory and simulation result of design are shown in QCA Designer Tool-2.0.

scholarly journals The Decomposition of DSP’s Control Logic Block for Power Reduction

2012 ◽  
Vol 16 (1) ◽  
Author(s):  
Borisav Jovanovic ◽  
Milunka Damnjanović
Keyword(s):  
Power Reduction ◽  
Control Logic ◽  
Logic Block

Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC

2017 ◽  
Vol 26 (05) ◽  
pp. 1750077 ◽  
Author(s):  
Anush Bekal ◽  
Shabi Tabassum ◽  
Manish Goswami
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Digital Control ◽  
Low Power Design ◽  
Cmos Technology ◽  
Control Logic ◽  
Control Block ◽  
Logic Block ◽  
External Clock ◽  
Asynchronous Sar

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Alok Kumar Mishra ◽  
Vaithiyanathan D. ◽  
Yogesh Pal ◽  
Baljit Kaur
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Power Saving ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Read Operation ◽  
Data Line ◽  
Sram Cell ◽  
Pmos Transistor

Purpose This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell. Design/methodology/approach The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate. Findings Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively. Originality/value The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

scholarly journals Improvement of SRAM stability using read and write assist techniques

2017 ◽  
Vol 6 (3) ◽  
pp. 78
Author(s):  
PullaReddy A ◽  
Sreenivasulu G ◽  
Veerabadra Chary R
Keyword(s):  
Process Variations ◽  
Primary Concern ◽  
Line Voltage ◽  
Read Operation ◽  
Sram Cell ◽  
Cell Stability ◽  
Pass Transistor ◽  
Circuit Techniques ◽  
The Stability ◽  
Future Technologies

The objective of this paper is to demonstrate how to improve the read stability of the SRAM cell using the read assist technique. SRAM cell stability is the primary concern for the present and future technologies due to process variations like Vt and Vdd scaling, etc. So it requires additional circuit techniques such as write and read to assist to improve the stability of SRAM memories. To accomplish the non-destructive read operation, we need to either weaken the pass transistor or strengthen the pull-up transistor during the read operation. Towards decrease of pass transistor strength, we implemented the lower word line voltage as read assist circuit. The lower word line voltage will help the selected and un-selected columns (for higher column mux options) during a read operation. But during write operation the lowered word line voltage scheme will impact the write operation. So, in order to improve the read margin we used read assist technique at the same time to ensure that write operation is successful we combined the negative bit line write assist scheme along with read assist technique. The proposed assist circuit gain the power and read margin improvement of 10%, 30% respectively. We observed the read margin analysis at process, voltage and temperature corners.

scholarly journals Low-power fast (LPF) SRAM cell for write/read operation

2011 ◽  
Vol 8 (18) ◽  
pp. 1473-1478 ◽  
Author(s):  
C. M. R. Prabhu ◽  
Ajay Kumar Singh
Keyword(s):  
Low Power ◽  
Read Operation ◽  
Sram Cell

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

scholarly journals Low-power reliable SRAM cell for write/read operation

2014 ◽  
Vol 11 (21) ◽  
pp. 20140913-20140913 ◽  
Author(s):  
C. M. R. Prabhu ◽  
Ajay Kumar Singh
Keyword(s):  
Low Power ◽  
Read Operation ◽  
Sram Cell

scholarly journals Intersectionality at the Grassroots

2019 ◽  
Author(s):  
Michael T. Heaney
Keyword(s):  
Social Justice ◽  
Collective Action ◽  
Washington Dc ◽  
Collective Action Frames ◽  
Lower Priority ◽  
History Of ◽  
A Priority ◽  
Action Frame

Intersectional activism is organizing that addresses more than one structure of oppression in the struggle for social justice. The rise of the Women’s March as a massive effort to mobilize women primarily on the basis of gender coincided with calls for it to pay greater attention to intersectionality. This study considers the effectiveness of the Women’s March at using intersectional activism as a collective action frame. Drawing on surveys conducted at Women’s March events in five cities and four other Washington, DC activist events in 2018, this study examines the extent to which activists think that the movements should place a priority on intersectional activism. The results show that participants in Women’s March events were more supportive of prioritizing intersectional activism than were activists at comparable protest events that were not mobilized using intersectional collective action frames. Furthermore, the results demonstrate that ideology may be a barrier to embracing intersectional activism, with more moderate and conservative activists placing a lower priority on intersectionality than did more liberal activists. Women’s March activists were more likely to prioritize intersectional activism if they were trans- or LGBTQIA+-identified, or if they had a history of backing intersectionally marginalized causes, than if they did not.

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