Utilizing device stacking for area efficient hardened SOI flip-flop designs

2014 ◽  
Author(s):  
J. S. Kauppila ◽  
T. D. Loveless ◽  
R. C. Quinn ◽  
J. A. Maharrey ◽  
M. L. Alles ◽  
...  
Keyword(s):  
Flip Flop ◽  
Device Stacking ◽  
Area Efficient

An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

2011 ◽  
Vol 58 (6) ◽  
pp. 3053-3059 ◽  
Author(s):  
Ryosuke Yamamoto ◽  
Chikara Hamanaka ◽  
Jun Furuta ◽  
Kazutoshi Kobayashi ◽  
Hidetoshi Onodera
Keyword(s):  
Flip Flop ◽  
Multiple Cell ◽  
Radiation Hard ◽  
Area Efficient

scholarly journals Low-power and area-efficient 9-transistor double-edge triggered flip-flop

2013 ◽  
Vol 10 (18) ◽  
pp. 20130639-20130639 ◽  
Author(s):  
S. Muthukumar ◽  
GoangSeog Choi
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Double Edge ◽  
Area Efficient

A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI

2014 ◽  
Vol 61 (4) ◽  
pp. 1881-1888 ◽  
Author(s):  
K. Kobayashi ◽  
K. Kubota ◽  
M. Masuda ◽  
Y. Manzawa ◽  
J. Furuta ◽  
...  
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Radiation Hard ◽  
Area Efficient
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