A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2014.2318326 ◽

2014 ◽

Vol 61 (4) ◽

pp. 1881-1888 ◽

Author(s):

K. Kobayashi ◽

K. Kubota ◽

M. Masuda ◽

Y. Manzawa ◽

J. Furuta ◽

...

Keyword(s):

Low Power ◽

Flip Flop ◽

Radiation Hard ◽

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A low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65 nm thin-BOX FD-SOI

2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS) ◽

10.1109/radecs.2013.6937380 ◽

2013 ◽

Author(s):

K. Kubota ◽

M. Masuda ◽

J. Furuta ◽

Y. Manzawa ◽

S. Kanda ◽

...

Keyword(s):

Low Power ◽

Flip Flop ◽

Radiation Hard ◽

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An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2011.2169457 ◽

2011 ◽

Vol 58 (6) ◽

pp. 3053-3059 ◽

Author(s):

Ryosuke Yamamoto ◽

Chikara Hamanaka ◽

Jun Furuta ◽

Kazutoshi Kobayashi ◽

Hidetoshi Onodera

Keyword(s):

Flip Flop ◽

Multiple Cell ◽

Radiation Hard ◽

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Low-power and area-efficient 9-transistor double-edge triggered flip-flop

IEICE Electronics Express ◽

10.1587/elex.10.20130639 ◽

2013 ◽

Vol 10 (18) ◽

pp. 20130639-20130639 ◽

Author(s):

S. Muthukumar ◽

GoangSeog Choi

Keyword(s):

Low Power ◽

Flip Flop ◽

Double Edge ◽

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A novel flip-flop based error free, area efficient and low power pipeline architecture for finite impulse recursive system

Cluster Computing ◽

10.1007/s10586-018-2513-4 ◽

2018 ◽

Vol 22 (S6) ◽

pp. 15137-15147 ◽

Author(s):

Raja Krishnamoorthy ◽

S. Saravanan

Keyword(s):

Low Power ◽

Pipeline Architecture ◽

Flip Flop ◽

Recursive System ◽

Free Area ◽

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Spin-Orbit-Torque Magnetic Tunnel Junction Transistor Based Area Efficient Low Power Non-Volatile Master-Slave Flip-Flop

International Journal of Emerging Trends in Engineering Research ◽

10.30534/ijeter/2020/109872020 ◽

2020 ◽

Vol 8 (7) ◽

pp. 3553-3556

Author(s):

Muthappa K A

Keyword(s):

Low Power ◽

Tunnel Junction ◽

Magnetic Tunnel Junction ◽

Flip Flop ◽

Junction Transistor ◽

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Area Efficient Low-Power Static Explicit-Pulsed Flip-Flop with Local Feedback

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635381 ◽

2006 ◽

Author(s):

W. L. Goh K. S. Yeo

Keyword(s):

Low Power ◽

Flip Flop ◽

Local Feedback ◽

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Low Power PVT robust area efficient pulse triggered Flip-Flop Design

2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE) ◽

10.1109/icrieece44171.2018.9009201 ◽

2018 ◽

Author(s):

P. Indira ◽

M. Kamaraju

Keyword(s):

Low Power ◽

Flip Flop ◽

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Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-0605013341 ◽

2016 ◽

Vol 06 (05) ◽

pp. 33-41

Author(s):

B. Sujita ◽

K. Padma Vasavi

Keyword(s):

Low Power ◽

Shift Register ◽

Flip Flop ◽

Vlsi Architectures ◽

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A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect

IEICE Transactions on Electronics ◽

10.1587/transele.e96.c.511 ◽

2013 ◽

Vol E96.C (4) ◽

pp. 511-517 ◽

Author(s):

Kuiyuan ZHANG ◽

Jun FURUTA ◽

Ryosuke YAMAMOTO ◽

Kazutoshi KOBAYASHI ◽

Hidetoshi ONODERA

Keyword(s):

Flip Flop ◽

Multiple Cell ◽

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Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.890 ◽

2009 ◽

Vol E92-A (3) ◽

pp. 890-899

Author(s):

Woo Joo KIM ◽

Sung Hee LEE ◽

Sun Young HWANG

Keyword(s):

Low Power ◽

Circuit Switching ◽

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