A flexible high performance 2-D discrete cosine transform IC

Author(s):  
L. Matterne ◽  
D. Chong ◽  
B. McSweeney ◽  
R. Woudsma
2013 ◽  
Vol 756-759 ◽  
pp. 3114-3120
Author(s):  
Jin Qi ◽  
Can Qun Yang ◽  
Cheng Chen ◽  
Qiang Wu ◽  
Tao Tang

Inverse Discrete Cosine Transform (IDCT) is an important operation for image and videos decompression. How to accelerate the IDCT algorithm has been frequently studied. Recently Intel has proposed Xeon Phi coprocessors based on the many integrated core (MIC) architecture. Xeon Phi is integrated with 61 cores and 512-bit SIMD extension within each core, thus providing very high performance. In this paper, we employ the Knights Corner (a beta version of Xeon Phi) to accelerate the IDCT algorithm. By employing the 512-bit SIMD instruction and data pre-fetching optimization, our implementation achieves (1) averagely 5.82 speedup over the none-SIMD version, (2) averagely 27.3% performance benefit with the data pre-fetching optimization, and (3) averagely 1.53 speedup on one Knights Corner coprocessor over the implementation on one octal-core Intel Xeon E5-2670 CPU.


Author(s):  
Zahraa Ch. Oleiwi ◽  
Dhiah Al-Shammary ◽  
Muntasir Al-Asfoor ◽  
Ayman Ibaida

Author(s):  
Mohammad R. Khosravi ◽  
Sadegh Samadi

AbstractHigh-performance remote sensing payload communication is a vital problem in air-borne and space-borne surveillance systems. Among different remote sensing imaging systems, video synthetic aperture radar (ViSAR) is a new technology with lots of principal and managerial data which should be compressed, aggregated, and communicated from a radar platform (or a network of radars) to a ground station through wireless links. In this paper, a new data aggregation technique is proposed towards efficient payload transmission in a network of aerial ViSAR vehicles. Our proposed method is a combination of a recent interpolation-based data hiding (IBDH) technique and visual data transformation process using discrete cosine transform (DCT) which is able to outperform the reference method in terms of data aggregation ability.


2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Shafqat Khan ◽  
Emmanuel Casseau ◽  
Daniel Menard

In this paper an efficient two-dimensional discrete cosine transform (DCT) operator is proposed for multimedia applications. It is based on the DCT operator proposed in Kovac and Ranganathan, 1995. Speed-up is obtained by using multimedia oriented subword parallelism (SWP). Rather than operating on a single pixel, the SWP-based DCT operator performs parallel computations on multiple pixels packed in word size input registers so that the performance of the operator is increased. Special emphasis is made to increase the coordination between pixel sizes and subword sizes to maximize resource utilization rate. Rather than using classical subword sizes (8, 16, and 32 bits), multimedia oriented subword sizes (8, 10, 12, and 16 bits) are used in the proposed DCT operator. The proposed SWP DCT operator unit can be used as a coprocessor for multimedia applications.


Programmable architectures like GPU based embedded system for video and imaging applications are widely used due to their high performance, as they allow flexibility for running customized functions. However these architectures do not allow reconfiguration of the architecture at run time and optimization of the hardware resources. This paper explores the FPGA based architecture suitable for all video CODEC standards used in multimedia applications which is both programmable and reconfigurable. The proposed architecture demonstrates an accelerator to perform two dimensional 8*8 discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT). The accelerator can be reconfigured to compute higher order two-dimensional DCT/IDCT according to different system requirements and is implemented on Xilinx Zynq evaluation board 7vx485tffg1157-1. The architecture is found to have a high scalability in terms of power and area. The synthesis results reads, 48% improvement in both dynamic and static power consumption, with optimal hardware utilization suitable for high performance video CODECs.


Author(s):  
Rahul Dixit ◽  
Amita Nandal ◽  
Arvind Dhaka ◽  
Vardan Agarwal ◽  
Yohan Varghese

Background: Nowadays information security is one of the biggest issues of social networks. The multimedia data can be tampered with, and the attackers can then claim its ownership. Image watermarking is a technique that is used for copyright protection and authentication of multimedia. Objective: We aim to create a new and more robust image watermarking technique to prevent illegal copying, editing and distribution of media. Method : The watermarking technique proposed in this paper is non-blind and employs Lifting Wavelet Transform on the cover image to decompose the image into four coefficient matrices. Then Discrete Cosine Transform is applied which separates a selected coefficient matrix into different frequencies and later Singular Value Decomposition is applied. Singular Value Decomposition is also applied to the watermarking image and it is added to the singular matrix of the cover image which is then normalized followed by the inverse Singular Value Decomposition, inverse Discrete Cosine Transform and inverse Lifting Wavelet Transform respectively to obtain an embedded image. Normalization is proposed as an alternative to the traditional scaling factor. Results: Our technique is tested against attacks like rotation, resizing, cropping, noise addition and filtering. The performance comparison is evaluated based on Peak Signal to Noise Ratio, Structural Similarity Index Measure, and Normalized Cross-Correlation. Conclusion: The experimental results prove that the proposed method performs better than other state-of-the-art techniques and can be used to protect multimedia ownership.


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