High-speed area-efficient recursive DFT/IDFT architectures

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328757 ◽

2004 ◽

Author(s):

Lan-Da Van ◽

Chih-Chyau Yang

Keyword(s):

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

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Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2019.8754423 ◽

2019 ◽

Author(s):

Diptesh Datta ◽

Piyush Dewangan ◽

Neelam Surana ◽

Joycee Mekie

Keyword(s):

Content Addressable Memory ◽

Ternary Content Addressable Memory ◽

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Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Materials Today Proceedings ◽

10.1016/j.matpr.2020.07.677 ◽

2020 ◽

Author(s):

A. Arunkumar Gudivada ◽

K. Jayaram Kumar ◽

Srinivasa Rao Jajula ◽

Durga Prasad Siddani ◽

Praveen Kumar Poola ◽

...

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Quantum Dot Cellular Automata ◽

Wallace Tree ◽

Wallace Tree Multiplier ◽

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High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378152 ◽

2007 ◽

Author(s):

A. Abdelgawad ◽

Magdy Bayoumi

Keyword(s):

Digital Signal ◽

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A low-power area-efficient wide-range offset calibration technique for high-speed high-resolution comparator

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2017.8333237 ◽

2017 ◽

Author(s):

Junxi Chen ◽

Shengqun Zheng ◽

Kai Sheng ◽

Weixin Gai ◽

Jianhua Feng

Keyword(s):

High Resolution ◽

Low Power ◽

Calibration Technique ◽

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Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs

2019 International Conference on Computer Communication and Informatics (ICCCI) ◽

10.1109/iccci.2019.8822204 ◽

2019 ◽

Author(s):

Aswini ◽

Ramesh Chinthala ◽

N.S. Murty

Keyword(s):

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High‐speed and area‐efficient scalable N ‐bit digital comparator

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2018.5562 ◽

2020 ◽

Vol 14 (4) ◽

pp. 450-458

Author(s):

Piyush Tyagi ◽

Rishikesh Pandey

Keyword(s):

Digital Comparator ◽

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Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm

IEICE Transactions on Electronics ◽

10.1093/ietele/e88-c.4.576 ◽

2005 ◽

Vol E88-C (4) ◽

pp. 576-581 ◽

Author(s):

S. MASUI

Keyword(s):

Low Power ◽

Design Optimization ◽

Rsa Algorithm ◽

Modular Multiplier ◽

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A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" ◽

10.23919/mixdes.2019.8787134 ◽

2019 ◽

Author(s):

Sara Ghafari ◽

Morteza Mousazadeh ◽

Abdollah Khoei ◽

Ali Dadashi

Keyword(s):

Low Area ◽

Tree Method ◽

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Design of Low Power, High Speed, Low Offset and Area Efficient Dynamic-Latch Comparator for SAR-ADC

2020 International Conference on Innovative Trends in Communication and Computer Engineering (ITCE) ◽

10.1109/itce48509.2020.9047792 ◽

2020 ◽

Author(s):

Kasi Bandla ◽

Harikrishnan A. ◽

Dipankar Pal

Keyword(s):

Low Power ◽

Sar Adc ◽

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