MHYNESYS II: Multi-stage hybrid Network on chip synthesis for Next Generation 3D IC Manycore

Author(s):  
O. Hammami ◽  
K. Hamwi
Author(s):  
Abdelkader Chaib ◽  
Fabrice Monteiro ◽  
Abbas Dandache

2020 ◽  
Vol 8 (6) ◽  
pp. 3393-3397

Various complex integrated circuits suffer from the issues like poor connectivity, higher energy consumption and design productivity. One of the best solutions could be Network-on-Chip architecture which could solve the above issues. The Network-on-Chip architecture should be modelled and simulated well to evaluate the performance and analyse the cost. This paper presents a method to validate the proposed Network-on-Chip architecture with direct sequence spread spectrum using BookSim simulator. This simulation aims at validating the network parameters like packet latency and network latency. The detailed architectural parameters are compared and presented in this paper.


2017 ◽  
Vol 35 (24) ◽  
pp. 5448-5455 ◽  
Author(s):  
Wei Tan ◽  
Huaxi Gu ◽  
Yintang Yang ◽  
Kun Wang ◽  
Xiaolu Wang

Complexity ◽  
2018 ◽  
Vol 2018 ◽  
pp. 1-11
Author(s):  
Juan Fang ◽  
Sitong Liu ◽  
Shijian Liu ◽  
Yanjin Cheng ◽  
Lu Yu

Burst growing IoT and cloud computing demand exascale computing systems with high performance and low power consumption to process massive amounts of data. Modern system platforms based on fundamental requirements encounter a performance gap in chasing exponential growth in data speed and amount. To narrow the gap, a heterogamous design gives us a hint. A network-on-chip (NoC) introduces a packet-switched fabric for on-chip communication and becomes the de facto many-core interconnection mechanism; it refers to a vital shared resource for multifarious applications which will notably affect system energy efficiency. Among all the challenges in NoC, unaware application behaviors bring about considerable congestion, which wastes huge amounts of bandwidth and power consumption on the chip. In this paper, we propose a hybrid NoC framework, combining buffered and bufferless NoCs, to make the NoC framework aware of applications’ performance demands. An optimized congestion control scheme is also devised to satisfy the requirement in energy efficiency and the fairness of big data applications. We use a trace-driven simulator to model big data applications. Compared with the classical buffered NoC, the proposed hybrid NoC is able to significantly improve the performance of mixed applications by 17% on average and 24% at the most, decrease the power consumption by 38%, and improve the fairness by 13.3%.


Author(s):  
Youhui Zhang ◽  
Peng Qu ◽  
Ziqiang Qian ◽  
Hongwei Wang ◽  
Weimin Zheng

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