A 9-bit 100-MS/s flash-SAR ADC without track-and-hold circuits

2012 International Symposium on Wireless Communication Systems (ISWCS) ◽

10.1109/iswcs.2012.6328494 ◽

2012 ◽

Cited By ~ 7

Author(s):

Young-Kyun Cho ◽

Jae-Ho Jung ◽

Kwang Chun Lee

Keyword(s):

Sar Adc

Get full-text (via PubEx)

Design of a high sensitivity and low power ultrasound receiver with a high-resolution SAR ADC for photoacoustic sensing and imaging

10.32657/10356/144400 ◽

2020 ◽

Author(s):

◽

Chuanshi Yang

Keyword(s):

High Resolution ◽

Low Power ◽

High Sensitivity ◽

Sar Adc ◽

Power Ultrasound

Get full-text (via PubEx)

SAR ADC Algorithm With Redundancy Using Pseudo-Silver-Ratio

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.137.222 ◽

2017 ◽

Vol 137 (2) ◽

pp. 222-228

Author(s):

Yutaro Kobayashi ◽

Takuya Arafune ◽

Shohei Shibuya ◽

Haruo Kobayashi

Keyword(s):

Sar Adc

Get full-text (via PubEx)

An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation

IEICE Transactions on Electronics ◽

10.1587/transele.e99.c.1331 ◽

2016 ◽

Vol E99.C (12) ◽

pp. 1331-1334 ◽

Cited By ~ 1

Author(s):

Guan-Wei JEN ◽

Wei-Liang LIN

Keyword(s):

Design Automation ◽

Sar Adc

Get full-text (via PubEx)

Comparison Of Capacitive DAC Architectures for Power and Area Efficient SAR ADC Designs

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401768 ◽

2021 ◽

Author(s):

Ankita Ahuja ◽

Komail Badami ◽

Cedric Barbelenet ◽

Stephane Emery

Keyword(s):

Sar Adc ◽

Capacitive Dac ◽

Area Efficient

Get full-text (via PubEx)

13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS

2021 IEEE International Solid- State Circuits Conference (ISSCC) ◽

10.1109/isscc42613.2021.9365927 ◽

2021 ◽

Author(s):

Gerd Kiene ◽

Alessandro Catania ◽

Ramon Overwater ◽

Paolo Bruschi ◽

Edoardo Charbon ◽

...

Keyword(s):

Quantum Computing ◽

Sar Adc

Get full-text (via PubEx)

An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993655 ◽

2017 ◽

Cited By ~ 12

Author(s):

Masaya Miyahara ◽

Akira Matsuzawa

Keyword(s):

Dynamic Range ◽

Open Loop ◽

Sar Adc ◽

Noise Shaping

Get full-text (via PubEx)

27.2 14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC

2021 IEEE International Solid- State Circuits Conference (ISSCC) ◽

10.1109/isscc42613.2021.9365863 ◽

2021 ◽

Author(s):

Kyojin Choo ◽

Hyochan An ◽

Dennis Sylvester ◽

David Blaauw

Keyword(s):

Charge Injection ◽

Sar Adc ◽

Capacitor Array

Get full-text (via PubEx)

High-level model based calibration technique design for SAR ADC

IOP Conference Series Materials Science and Engineering ◽

10.1088/1757-899x/1032/1/012050 ◽

2021 ◽

Vol 1032 ◽

pp. 012050

Author(s):

M N Skripnichenko

Keyword(s):

Sar Adc ◽

Calibration Technique ◽

Model Based ◽

Level Model ◽

High Level

Get full-text (via PubEx)

A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2021.3059857 ◽

2021 ◽

pp. 1-9

Author(s):

Jian Liu ◽

Shubin Liu ◽

Ruixue Ding ◽

Zhangming Zhu

Keyword(s):

Sar Adc ◽

Conversion Mode

Get full-text (via PubEx)

A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431475 ◽

2021 ◽

Author(s):

Yuting Shen ◽

Hanyue Li ◽

Haoming Xin ◽

Eugenio Cantatore ◽

Pieter Harpe

Keyword(s):

Low Cost ◽

Sar Adc ◽

Mismatch Error

Get full-text (via PubEx)