A 117-mm/sup 2/ 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications

1996 ◽  
Vol 31 (11) ◽  
pp. 1575-1583 ◽  
Author(s):  
Tae-Sung Jung ◽  
Young-Joon Choi ◽  
Kang-Deog Suh ◽  
Byung-Hoon Suh ◽  
Jin-Ki Kim ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Mass Storage ◽  
Nand Flash Memory

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

2003 ◽  
Vol 38 (11) ◽  
pp. 1934-1942 ◽  
Author(s):  
June Lee ◽  
Sung-Soo Lee ◽  
Oh-Suk Kwon ◽  
Kyeong-Han Lee ◽  
Dae-Seok Byeon ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Mass Storage ◽  
Nand Flash Memory

scholarly journals A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 759
Author(s):  
Michele Favalli ◽  
Cristian Zambelli ◽  
Alessia Marelli ◽  
Rino Micheloni ◽  
Piero Olivo
Keyword(s):  
Flash Memory ◽  
Cost Effective ◽  
Processing Technique ◽  
Nand Flash ◽  
Mass Storage ◽  
Nand Flash Memory ◽  
Signal Processing Technique ◽  
Memory Integration ◽  
Randomization Scheme ◽  
Commercial Off The Shelf

Data randomization has been a widely adopted Flash Signal Processing technique for reducing or suppressing errors since the inception of mass storage platforms based on planar NAND Flash technology. However, the paradigm change represented by the 3D memory integration concept has complicated the randomization task due to the increased dimensions of the memory array, especially along the bitlines. In this work, we propose an easy to implement, cost effective, and fully scalable with memory dimensions, randomization scheme that guarantees optimal randomization along the wordline and the bitline dimensions. At the same time, we guarantee an upper bound on the maximum length of consecutive ones and zeros along the bitline to improve the memory reliability. Our method has been validated on commercial off-the-shelf TLC 3D NAND Flash memory with respect to the Raw Bit Error Rate metric extracted in different memory working conditions.

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

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