A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2019.2926191 ◽

2019 ◽

Vol 54 (9) ◽

pp. 2487-2500 ◽

Author(s):

Fahim ur Rahman ◽

Greg Taylor ◽

Visvesh Sathe

Keyword(s):

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Integral Impact of PVT variation with NBTI degradation on dynamic and static SRAM performance metrics

International Journal of Electronics ◽

10.1080/00207217.2021.1908628 ◽

2021 ◽

Author(s):

Siona Menezes Picardo ◽

Jani Babu Shaik ◽

Nilesh Goel ◽

Sonal Singhal

Keyword(s):

Performance Metrics ◽

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A novel PVT‐variation ‐ tolerant Schmitt‐trigger‐based 12T SRAM cell with improved write ability and high I ON /I OFF ratio in sub‐threshold region

International Journal of Circuit Theory and Applications ◽

10.1002/cta.3134 ◽

2021 ◽

Author(s):

Monica Gupta ◽

Kirti Gupta ◽

Neeta Pandey

Keyword(s):

Schmitt Trigger ◽

Threshold Region ◽

Sram Cell ◽

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A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351313 ◽

2018 ◽

Author(s):

Lu Zhang ◽

Jin Zhang ◽

Yuan Wang ◽

Xing Zhang ◽

Ru Huang

Keyword(s):

Neuron Circuit ◽

Silicon Neuron ◽

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Design of Frequency Multiplier with Delay Locked Loop that is insensitive to PVT Variation and prescreen Harmonic Lock

10.1109/icufn49451.2021.9528610 ◽

2021 ◽

Author(s):

Ho Won Kim ◽

Kang Yoon Lee

Keyword(s):

Frequency Multiplier ◽

Delay Locked Loop ◽

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Circuit Techniques for PVT Variation Tolerance

Variation Tolerant On-Chip Interconnects ◽

10.1007/978-1-4614-0131-5_8 ◽

2011 ◽

pp. 127-156 ◽

Author(s):

Ethiopia Enideg Nigussie

Keyword(s):

Circuit Techniques ◽

Variation Tolerance ◽

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A Slew Rate Variation Compensated $2\times$ VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2018.2837110 ◽

2019 ◽

Vol 66 (1) ◽

pp. 116-120 ◽

Author(s):

Tzung-Je Lee ◽

Tsung-Yi Tsai ◽

Wei Lin ◽

U-Fat Chio ◽

Chua-Chin Wang

Keyword(s):

Detection Method ◽

Rate Variation ◽

Slew Rate ◽

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Multi-Ported Register File for Reducing the Impact of PVT Variation

IEICE Transactions on Electronics ◽

10.1093/ietele/e89-c.3.356 ◽

2006 ◽

Vol E89-C (3) ◽

pp. 356-363

Author(s):

Y. IKEDA

Keyword(s):

Register File ◽

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Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2016.2643618 ◽

2017 ◽

Vol 25 (4) ◽

pp. 1444-1454 ◽

Author(s):

Innocent Agbo ◽

Mottaqiallah Taouil ◽

Daniel Kraak ◽

Said Hamdioui ◽

Halil Kukner ◽

...

Keyword(s):

Sense Amplifier ◽

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A sub-1V, 120 nW, PVT-variation Tolerant, Tunable and Scalable Voltage Reference with 60 d

IEEE Transactions on Nanotechnology ◽

10.1109/tnano.2017.2656161 ◽

2017 ◽

pp. 1-1 ◽

Author(s):

Baibhab Chatterjee ◽

Nirmoy Modak ◽

Anvesha Amaravati ◽

Deep Mistry ◽

Devarshi Das ◽

...

Keyword(s):

Voltage Reference ◽

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A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits

2014 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2014.6865360 ◽

2014 ◽

Author(s):

Lih-Yih Chiou ◽

Chi-Ray Huang ◽

Ming-Hung Wu

Keyword(s):

Timing Error ◽

Power Efficient ◽

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