A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control

2020 ◽  
Vol 55 (4) ◽  
pp. 1043-1050 ◽  
Author(s):  
Chen-Ting Ko ◽  
Ting-Kuei Kuan ◽  
Ruei-Pin Shen ◽  
Chih-Hsien Chang
2015 ◽  
Vol 62 (12) ◽  
pp. 2817-2828 ◽  
Author(s):  
Soon-Won Kwon ◽  
Joon-Yeong Lee ◽  
Jinhee Lee ◽  
Kwangseok Han ◽  
Taeho Kim ◽  
...  

2018 ◽  
Vol 2018 ◽  
pp. 1-14
Author(s):  
Zhibin Luo ◽  
Jicheng Ding ◽  
Lin Zhao

The global navigation satellite system (GNSS) has been widely used in both military and civil fields. This study focuses on enhancing the carrier tracking ability of the phase-locked loop (PLL) in GNSS receivers for high-dynamic application. The PLL is a very popular and practical approach for tracking the GNSS carrier signal which propagates in the form of electromagnetic wave. However, a PLL with constant coefficient would be suboptimal. Adaptive loop noise bandwidth techniques proposed by previous researches can improve PLL tracking behavior to some extent. This paper presents a novel PLL with an adaptive loop gain control filter (AGCF-PLL) that can provide an alternative. The mathematical model based on second- and third-order PLL was derived. The error characteristics of the AGCF-PLL were also derived and analyzed under different signal conditions, which mainly refers to the different combinations of carrier phase dynamic and signal strength. Based on error characteristic curves, the optimal loop gain control method has been achieved to minimize tracking error. Finally, the completely adaptive loop gain control algorithm was designed. Comparable test results and analysis using the new method, conventional PLL, FLL-assisted PLL, and FAB-LL demonstrate that the AGCF-PLL has stronger adaptability to high target movement dynamic.


2021 ◽  
Author(s):  
Chembiyan Thambidurai

Fractional-N charge pump phase locked loops (PLLs) suffer from the problem of increased in-band phase noise due to charge pump non-linearity caused by UP/DN chargepump current mismatch. Existing techniques that resolve this problem by introducing phase offset between reference and divide signals cause large reference spurs or increase jitter at PLL output. A very low reference spur phase offset technique is proposed in this work. It produces the lowest reference spurs compared to previously published works. A detailed comparison of the reference spurs caused by the different techniques to introduce phase offset is presented. Simulation results show that the reference spur level generated at the PLL output after applying the proposed technique is 26 dB lower than the existing techniques in the presence of 5% chargepump current mismatch.<br>


1983 ◽  
Author(s):  
Shigeki Inoue ◽  
Yoshimi Iso ◽  
Harushige Nakagaki ◽  
Masafumi Nakamura

Sign in / Sign up

Export Citation Format

Share Document