A 0.8∼1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference spur suppression

2017 ◽  
Author(s):  
Ruixin Wang ◽  
Fa Foster Dai
Keyword(s):  
Ring Oscillator ◽  
Reference Spur ◽  
Multi Phase

Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers

2008 ◽  
Vol 43 (3) ◽  
pp. 656-671 ◽  
Author(s):  
Ahmad Mirzaei ◽  
Mohammad E. Heidari ◽  
Rahim Bagheri ◽  
Asad A. Abidi
Keyword(s):  
Ring Oscillator ◽  
Frequency Dividers ◽  
Multi Phase

A 3 mW 1.2–3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth

2018 ◽  
Vol 27 (08) ◽  
pp. 1850117 ◽  
Author(s):  
Jili Zhang ◽  
Yu Li ◽  
Shengxi Diao ◽  
Xuefei Bai ◽  
Fujiang Lin
Keyword(s):  
Low Frequency ◽  
Cmos Process ◽  
Clock Generator ◽  
Loop Filter ◽  
Time Period ◽  
Loop Bandwidth ◽  
Reference Spur ◽  
On Chip ◽  
Multi Phase ◽  
Better Than

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of [Formula: see text]-stage ring-VCO with a resolution of [Formula: see text] in a time period of [Formula: see text]. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40[Formula: see text]nm CMOS process and operates from 1.2[Formula: see text]GHz to 3.6[Formula: see text]GHz with 8-phase outputs. The total lock time is less than 3[Formula: see text][Formula: see text]s including calibration and PLL closed-loop locking processes. Operating at 3.2[Formula: see text]GHz, the in-band phase noise is better than [Formula: see text][Formula: see text]dBc/Hz and root-mean square (RMS) jitter integrated from 10[Formula: see text]KHz to 100[Formula: see text]MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5[Formula: see text]ps and [Formula: see text][Formula: see text]dBc/Hz, respectively. The clock generator consumes only 3[Formula: see text]mW from 1.1[Formula: see text]V supply at high-frequency end and 1.6[Formula: see text]mW at low-frequency end. The active area is only 0.04[Formula: see text]mm2 including on-chip loop filter and auto-calibration circuits.

Some Applications of the U. S. Steel MVEM

1973 ◽  
Vol 31 ◽  
pp. 4-5
Author(s):  
J. S. Lally ◽  
L. E. Thomas ◽  
R. M. Fisher
Keyword(s):  
Electron Diffraction ◽  
Debye Temperature ◽  
Metals And Alloys ◽  
Critical Voltage ◽  
Dynamical Diffraction ◽  
Phase Structures ◽  
Structure Factors ◽  
Local Bonding ◽  
Diffraction Phenomenon ◽  
Multi Phase

A variety of materials containing many different microstructures have been examined with the USS MVEM. Three topics have been selected to illustrate some of the more recent studies of diffraction phenomena and defect, grain and multi-phase structures of metals and minerals.(1) Critical Voltage Effects in Metals and Alloys - This many-beam dynamical diffraction phenomenon, in which some Bragg resonances vanish at certain accelerating voltages, Vc, depends sensitively on the spacing of diffracting planes, Debye temperature θD and structure factors. Vc values can be measured to ± 0.5% in the HVEM ana used to obtain improved extinction distances and θD values appropriate to electron diffraction, as well as to probe local bonding effects and composition variations in alloys.

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