A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer

High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.

Optimization of frequency settling time of PLL using 3rd MASH Sigma Delta Modulator

To reduce settling time of PLL, an attempt to optimize the parameters has been proposed in this paper. The transient responses of various Phase Locked Loop (PLL) frequency synthesizer have been comparied with their active and passive poles effect. These results are presented on a type-II 3rd order PLL frequency synthesizer employing a 3rd order MASH sigma delta modulator. The simulation results show the improved performance of the fractional frequency synthesizer for the communication system. These results have been simulated using Advanced Design System(ADS) tool.

A Novel Design of high performance low power phase frequency Detector for CMOS PLL frequency Synthesizer

Aims: A high performance low power phase frequency detector is designed and simulated. The various different parameters of the circuit are obtained through various type of simulations. We worked mainly upon the power dissipation, power supply, input frequency range and its area. The proposed PFD will have the locking capability i.e. to lock at the edges either on the rising or falling edge w.r.t the reference and the feedback signal. The proposed design will have the very high performance and ultra-low phase noise. It has the added advantage of low cost and the compact size. Objective: The primary objective is to design a low power phase frequency detector for CMOS PLL Frequency Synthesizer using lows power technique. Method: The pass transistor logic is used in the circuit to eliminate the reset path. By this change of the path the operating frequency and operating speed both are increased in the proposed design. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD design will have a less number of transistors and also a low consumption of power. The output pulses of the PFD at phase difference of 0, 0,п/2, п, 3п/2, 2п will have its average voltage as 0, VDD and VDD/2. The proposed phase detector will perfectly detect the phase difference between two signals so that the harmonics problem can be minimized. Result: The proposed design is having its operating frequency as 5GHz over the conventional one which has its frequency as 800MHz. Power dissipation in the proposed design is reduced due to less number of transistors used as compared with the conventional one. The operating region has become much wider for proposed design as it is having operating frequency much higher than that of the conventional one. Conclusion: The proposed PFD will increase the locking capability on the both rise and fall edge w.r.t. the reference and the feedback signal. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD circuit will have a less number of transistors and also a low consumption of power 7.14 mW.