Gain-Coupled 4x56 Gb/s EML Array with Optimized Bonding-Wire Inductance

Author(s):  
Shuhan Yang ◽  
Changzheng Sun ◽  
Bing Xiong ◽  
Jian Wang ◽  
Hao Zhibiao ◽  
...  
Keyword(s):  
2008 ◽  
Vol 85 (8) ◽  
pp. 1795-1803 ◽  
Author(s):  
C.J. Hang ◽  
I. Lum ◽  
J. Lee ◽  
M. Mayer ◽  
C.Q. Wang ◽  
...  
Keyword(s):  

2011 ◽  
Vol 51 (12) ◽  
pp. 2250-2256 ◽  
Author(s):  
Hyung-Giun Kim ◽  
Taeg-Woo Lee ◽  
Eun-Kyun Jeong ◽  
Won-Yong Kim ◽  
Sung-Hwan Lim

Author(s):  
Yong Xiao ◽  
Xiaoyan Wang ◽  
Kuanyi Zhu ◽  
Xiaoyu Ge ◽  
Jingna Sun

2019 ◽  
Vol 2019 (1) ◽  
pp. 000603-000608
Author(s):  
Chi Zhang ◽  
Yifan Tan ◽  
Zhizhao Huang ◽  
Cai Chen ◽  
Yong Kang

Abstract The stacked substrate packaging technology is a new 3D power loop structure utilizing multiple layer DBC to achieve ultra-low parasitic for the fast switching SiC device. This structure has a different geometry on interconnection between chips and substrate contrasting to the conventional module design, which needs optimization on the interconnection for the reliability consideration of this new structure. Analytical models of different bonding wire shapes and DBC structures were developed to calculate the von-mise stress on each model under thermal cycling simulation. The simulation results show that the stress on bonding wire reaches minimum when welding point located at the center of the top DBC substrate and the stress decreases when DBC top copper layer thickness increases or ceramic layer thickness decreases. Moreover, bonding wires with smaller diameter, certain peak height and width show lower stress and strain. Furthermore, thermal cycling tests were done on samples with same geometries of analytical models, and the wire pull test results showed consistency with the stress calculation results which verifying the optimum wire shape and DBC structure for the stacked substrate packaging.


2015 ◽  
Vol 2015 (1) ◽  
pp. 000394-000398
Author(s):  
William G. Crockett

Since around 2008, the shift from Gold (Au) bonding wire to Copper (Cu) bonding wire has been taking place, full scale, with the aim of reducing costs. When compared with Au, Cu wire presents challenges in reliability and repeatable bonding characteristics in terms of chemical stability, which is required in high reliability applications. Therefore Cu wire adoption in automotive and industrial semiconductors has been limited. Conventionally the market for Cu bonding wires has been divided into two types: bare Cu wires (high purity) and Palladium coated copper (PCC) bonding wires. These wires have yet to satisfy the required characteristics for high reliability products such as industrial and automotive electronics. A new breed of alternative bonding wires has been developed to offer performance advantages for high reliability applications compared to bare copper wire and PCC wire. Cu alloy wire and Ag alloy wires continue their market introduction for advanced bonding applications, where bare Cu and PCC wires have known limitations.


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