On the design of low noise and power efficient onchip oscillators

Author(s):  
Dwight Jose Cabrera Salas ◽  
Jose Vieira do Vale Neto
Keyword(s):  
2011 ◽  
Vol 16 (4) ◽  
pp. 66-72
Author(s):  
V.Sh. Melikyan ◽  
A.A. Durgaryan ◽  
H.P. Petrosyan ◽  
A.G. Stepanyan

A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead


2019 ◽  
Vol 55 (5) ◽  
pp. 1-10 ◽  
Author(s):  
Hee Sung Lee ◽  
Seung Hun Kim ◽  
Tae Hwan Jang ◽  
Hee-Gyum Park ◽  
Byoung-Chul Min ◽  
...  

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