Power-Efficient Spin-Torque Nano-Oscillator-Based Wireless Communication With CMOS High-Gain Low-Noise Transmitter and Receiver

2019 ◽  
Vol 55 (5) ◽  
pp. 1-10 ◽  
Author(s):  
Hee Sung Lee ◽  
Seung Hun Kim ◽  
Tae Hwan Jang ◽  
Hee-Gyum Park ◽  
Byoung-Chul Min ◽  
...  
2012 ◽  
Vol 2012 ◽  
pp. 1-15
Author(s):  
Apratim Roy

A new microwave receiver configuration which transmits reference pulses embedded in data streams for synchronization is analyzed with a 90-nm IBM CMOS standard. A two-stage cascode low-noise amplifier (LNA) is proposed for the receiver front-end which is matched by a passive network to save on power-expensive matching techniques. The amplifier exploits a double-differential topology and achieves a below 4 dB noise figure near the center frequency. The overall 3-dB bandwidth is 3.3 GHz with peaking up to 20.5 dB in the -band. The back-end of the receiver is implemented through an adjustable analog window-detection circuit. It avoids the use of control voltage generators and sample-hold (S/H) blocks to save electronic overhead and is simulated with a 0.1~2.0 Gbps pulse stream. The achieved speed-to-power ratio for the back-end has a maximum limit of 266 GHz/W. When compared against simulated results of published literature, the proposed designs show improved performance in terms of small-signal gain, noise, speed, and power dissipation.


2012 ◽  
Vol 2 (3) ◽  
Author(s):  
Apratim Roy ◽  
S. Rashid

AbstractIn this paper, a single-stage deep sub-micron wideband amplifier (LNA) using a reactive resonance tank and passive port-matching techniques is demonstrated operating in the microwave frequency range (K band). A novel power-efficient bandwidth (BW) regulation technique is proposed by incorporating a small impedance in the resonance tank of the amplifier configuration. It manifests a forward gain in the range of 5.9–10.7 dB covering a message bandwidth of 10.6–6.3 GHz. With regulation, input-output reflection parameters (S 11, S 22) and noise figure can be manipulated by −12.7 dB, −22.7 dB and 0.36 dB, respectively. Symmetric regulation is achieved for bandwidth and small signal gain with respect to moderate tank impedance (36.5% and −26.8%, respectively) but the effect on noise contribution remains relatively low (increase of 7% from a base value of 2.39 dB). The regulated architecture, when analyzed with 90 nm silicon CMOS process, supports low power (9.1 mW) on-chip communication. The circuit is tested with a number of combinations for tank (drain) impedance to verify the efficiency of the proposed technique and achieves better figures of merit when compared with published literature.


2011 ◽  
Vol E94-C (10) ◽  
pp. 1548-1556 ◽  
Author(s):  
Takana KAHO ◽  
Yo YAMAGUCHI ◽  
Kazuhiro UEHARA ◽  
Kiyomichi ARAKI

2010 ◽  
Vol 7 (23) ◽  
pp. 1686-1693 ◽  
Author(s):  
Ehsan Kargaran ◽  
Hojat Khosrowjerdi ◽  
Karim Ghaffarzadegan ◽  
Hooman Nabovati
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