A VLSI implementation of an interface for a dual protocol high speed active bus
2017 ◽
Vol 9
(3)
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pp. 216-221
2019 ◽
Vol 78
(13)
◽
pp. 17673-17699
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Keyword(s):
2010 ◽
Vol 5
(4)
◽
pp. 475-482
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