A floating-gate memory cell for continuous-time programming

Author(s):  
Brandon Rumberg ◽  
David W. Graham
2021 ◽  
pp. 108062
Author(s):  
Maksym Paliy ◽  
Tommaso Rizzo ◽  
Piero Ruiu ◽  
Sebastiano Strangio ◽  
Giuseppe Iannaccone

2021 ◽  
Author(s):  
Side Song ◽  
Guozhu Liu ◽  
Qi He ◽  
Xiang Gu ◽  
Genshen Hong ◽  
...  

Abstract In this paper, the combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail, the results indicate that: 1.The programmed flash cells with a prior appropriate number of program and erase cycling stress exhibit much smaller threshold voltage shift than their counterpart in response to radiation, which is mainly ascribed to the recombination of trapped electrons (introduced by cycling stress) and trapped holes (introduced by irradiation) in the oxide surrounding the floating gate; 2.The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in both of the programmed state and erased state; 3. Radiation is more likely to induce interface generation in programmed state than in erased state. This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.


2021 ◽  
Vol 11 (1) ◽  
pp. 4
Author(s):  
Brandon Rumberg ◽  
Spencer Clites ◽  
Haifa Abulaiha ◽  
Alexander DiLello ◽  
David Graham

Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array.


2018 ◽  
Vol 29 (10) ◽  
pp. 4782-4790 ◽  
Author(s):  
Farnood Merrikh-Bayat ◽  
Xinjie Guo ◽  
Michael Klachko ◽  
Mirko Prezioso ◽  
Konstantin K. Likharev ◽  
...  

2008 ◽  
Vol 55 (6) ◽  
pp. 3000-3008 ◽  
Author(s):  
Nicola Wrachien ◽  
Andrea Cester ◽  
Rosario Portoghese ◽  
Cosimo Gerardi

1997 ◽  
Vol 71 (14) ◽  
pp. 2038-2040 ◽  
Author(s):  
C. D. Chen ◽  
Y. Nakamura ◽  
J. S. Tsai

Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.


2009 ◽  
Vol 48 (4) ◽  
pp. 04C153 ◽  
Author(s):  
Kosuke Ohara ◽  
Yukiharu Uraoka ◽  
Takashi Fuyuki ◽  
Ichiro Yamashita ◽  
Toshitake Yaegashi ◽  
...  

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