CMOS image sensor with adaptive readout scheme for low power applications

Author(s):  
Varun Kumar ◽  
Bibhudatta Satapathy ◽  
Wilfred Kisku ◽  
Amandeep Kaur ◽  
Deepak Mishra
Author(s):  
Bing Zhang ◽  
Congzhen Hu ◽  
Junhua Lai ◽  
Youze Xin ◽  
Zhuoqi Guo ◽  
...  

2014 ◽  
Vol 23 (2) ◽  
pp. 87-93
Author(s):  
Ju-Yeong Kim ◽  
Jeongyeob Kim ◽  
Myunghan Bae ◽  
Sung-Hyun Jo ◽  
Minho Lee ◽  
...  

2015 ◽  
Vol 50 (10) ◽  
pp. 2419-2430 ◽  
Author(s):  
Numa Couniot ◽  
Guerric de Streel ◽  
Francois Botman ◽  
Angelo Kuti Lusala ◽  
Denis Flandre ◽  
...  

Author(s):  
Minho Kwon ◽  
Seunghyun Lim ◽  
Hyeokjong Lee ◽  
Il-Seon Ha ◽  
Moo-Young Kim ◽  
...  

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).


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