Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures

2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006) ◽

10.1109/reconf.2006.307764 ◽

2006 ◽

Author(s):

Ameet Chavan ◽

Gaurav Dukle ◽

Ben Graniello ◽

Eric MacDonald

Keyword(s):

Low Power ◽

Reconfigurable Architectures ◽

Flip Flop ◽

Ultra Low Power ◽

Subthreshold Logic

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Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

10.1109/icecs53924.2021.9665485 ◽

2021 ◽

Author(s):

Yugal Maheshwari ◽

Kleber Stangherlin ◽

Derek Wright ◽

Manoj Sachdev

Keyword(s):

Low Power ◽

Single Phase ◽

Flip Flop ◽

Ultra Low Power

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Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2018.2875089 ◽

2019 ◽

Vol 54 (2) ◽

pp. 550-559 ◽

Author(s):

Yunpeng Cai ◽

Anand Savanth ◽

Pranay Prabhat ◽

James Myers ◽

Alex S. Weddell ◽

...

Keyword(s):

Low Power ◽

Single Phase ◽

Flip Flop ◽

Ultra Low Power

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Ultra-low power subthreshold flip-flop design

2009 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2009.5118070 ◽

2009 ◽

Author(s):

Sagi Fisher ◽

Adam Teman ◽

Dmitry Vaysman ◽

Alexander Gertsman ◽

Orly Yadid-Pecht ◽

...

Keyword(s):

Low Power ◽

Flip Flop ◽

Ultra Low Power

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High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application

2010 IEEE International SOI Conference (SOI) ◽

10.1109/soi.2010.5641061 ◽

2010 ◽

Author(s):

Chun-Yu Chen ◽

Jyi-Tsong Lin ◽

Meng-Hsueh Chiang ◽

Keunwoo Kim

Keyword(s):

Low Power ◽

High Performance ◽

Ultra Low Power ◽

Subthreshold Logic

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Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

IEEE Transactions on Nanotechnology ◽

10.1109/tnano.2019.2929233 ◽

2019 ◽

Vol 18 ◽

pp. 756-761

Author(s):

Ahmad Karimi ◽

Abdalhossein Rezai ◽

Mohammad Mahdi Hajhashemkhani

Keyword(s):

Low Power ◽

Flip Flop ◽

Ultra Low Power ◽

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Temperature-Adaptive Energy Reduction for Ultra-Low Power-Supply-Voltage Subthreshold Logic Circuits

2007 14th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2007.4511231 ◽

2007 ◽

Author(s):

Ranjith Kumar ◽

Volkan Kursun

Keyword(s):

Low Power ◽

Power Supply ◽

Supply Voltage ◽

Logic Circuits ◽

Energy Reduction ◽

Power Supply Voltage ◽

Ultra Low Power ◽

Subthreshold Logic

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Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2013.2295026 ◽

2014 ◽

Vol 61 (6) ◽

pp. 1755-1765 ◽

Author(s):

Djaafar Chabi ◽

Weisheng Zhao ◽

Erya Deng ◽

Yue Zhang ◽

Nesrine Ben Romdhane ◽

...

Keyword(s):

Low Power ◽

Power Gating ◽

Flip Flop ◽

Ultra Low Power

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Robust subthreshold logic for ultra-low power operation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.920822 ◽

2001 ◽

Vol 9 (1) ◽

pp. 90-99 ◽

Author(s):

H. Soeleman ◽

K. Roy ◽

B.C. Paul

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Power Operation ◽

Subthreshold Logic

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Ultra-low power NAND based multiplexer and flip-flop

2013 Nirma University International Conference on Engineering (NUiCONE) ◽

10.1109/nuicone.2013.6780110 ◽

2013 ◽

Author(s):

Ishan Varun ◽

Tarun Kumar Gupta

Keyword(s):

Low Power ◽

Flip Flop ◽

Ultra Low Power

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A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power

Integration ◽

10.1016/j.vlsi.2017.09.002 ◽

2018 ◽

Vol 60 ◽

pp. 160-166 ◽

Author(s):

Ahmad Karimi ◽

Abdalhossein Rezai ◽

Mohammad Mahdi Hajhashemkhani

Keyword(s):

Low Power ◽

Leakage Power ◽

Flip Flop ◽

Ultra Low Power ◽

Power Pulse ◽

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