subthreshold logic Latest Research Papers

Ultra-low power subthreshold logic with Germanium junctionless transistors

Semiconductor Science and Technology ◽

10.1088/1361-6641/abfd16 ◽

2021 ◽

Author(s):

Pradeep Shrivas ◽

Nivedita Jaiswal ◽

Sandeep Semwal ◽

Abhinav Kranti

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Junctionless Transistors ◽

Subthreshold Logic

Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate

IEEE Transactions on Electron Devices ◽

10.1109/ted.2021.3107817 ◽

2021 ◽

pp. 1-5

Author(s):

Te-Kuang Chiang

Keyword(s):

Logic Gate ◽

Current Model ◽

Subthreshold Current ◽

Noise Margin ◽

Subthreshold Logic

Elliptical nanowire FET: Modeling the short-channel subthreshold current caused by interface-trapped-charge and its evaluation for subthreshold logic gate

Superlattices and Microstructures ◽

10.1016/j.spmi.2020.106751 ◽

2021 ◽

Vol 149 ◽

pp. 106751

Author(s):

Te-Kuang Chiang

Keyword(s):

Logic Gate ◽

Short Channel ◽

Subthreshold Current ◽

Subthreshold Logic ◽

Trapped Charge

Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate

Microelectronics Journal ◽

10.1016/j.mejo.2020.104893 ◽

2020 ◽

Vol 104 ◽

pp. 104893

Author(s):

Te-kuang Chiang

Keyword(s):

Logic Gate ◽

Current Model ◽

Subthreshold Current ◽

Subthreshold Logic ◽

Trapped Charge

A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates

IEEE Transactions on Nanotechnology ◽

10.1109/tnano.2018.2803845 ◽

2018 ◽

Vol 17 (3) ◽

pp. 424-431 ◽

Cited By ~ 1

Author(s):

Hong-Wun Gao ◽

Yeong-Her Wang ◽

Te-Kuang Chiang

Keyword(s):

Low Power ◽

Logic Gates ◽

Power Model ◽

Double Gate ◽

New Device ◽

Dc Power ◽

Device Parameter ◽

Low Power Cmos ◽

Subthreshold Logic

Subthreshold logic for low-area and energy efficient true random number generator

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373081 ◽

2018 ◽

Author(s):

Mathieu Coustans ◽

Abdelkarim Cherkaoui ◽

Laurent Fesquet ◽

Christian Terrier ◽

Stephanie Salgado ◽

...

Keyword(s):

Energy Efficient ◽

Random Number ◽

Random Number Generator ◽

Number Generator ◽

True Random Number Generator ◽

Low Area ◽

Subthreshold Logic

Estimation methods for static noise margins in CMOS subthreshold logic circuits

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design Chip on the Sands - SBCCI '17 ◽

10.1145/3109984.3109998 ◽

2017 ◽

Author(s):

Felipe T. Bortolon ◽

Fernando G. Moraes ◽

Matheus T. Moreira ◽

Sergio Bampi

Keyword(s):

Logic Circuits ◽

Estimation Methods ◽

Subthreshold Logic ◽

Static Noise

Performance Prospects of Subthreshold Logic Circuits

MOS Devices for Low-Voltage and Low-Energy Applications ◽

10.1002/9781119107361.ch3 ◽

2016 ◽

pp. 12-13

Keyword(s):

Logic Circuits ◽

Subthreshold Logic

A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

IEEE Transactions on Electron Devices ◽

10.1109/ted.2016.2612658 ◽

2016 ◽

Vol 63 (11) ◽

pp. 4209-4217 ◽

Cited By ~ 6

Author(s):

Te-Kuang Chiang

Keyword(s):

Logic Gate ◽

Device Physics ◽

New Device ◽

Noise Margin ◽

Surrounding Gate ◽

Subthreshold Logic

Design and estimation of power and delay using high Vth nmos under subthreshold logic operation of SRAM onebit model

2016 International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES) ◽

10.1109/scopes.2016.7955750 ◽

2016 ◽

Author(s):

T. Vasudeva Reddy ◽

B. K. Madhavi

Keyword(s):

Logic Operation ◽

Subthreshold Logic

subthreshold logic
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Ultra-low power subthreshold logic with Germanium junctionless transistors

Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate

Elliptical nanowire FET: Modeling the short-channel subthreshold current caused by interface-trapped-charge and its evaluation for subthreshold logic gate

Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate

A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates

Subthreshold logic for low-area and energy efficient true random number generator

Estimation methods for static noise margins in CMOS subthreshold logic circuits

Performance Prospects of Subthreshold Logic Circuits

A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

Design and estimation of power and delay using high Vth nmos under subthreshold logic operation of SRAM onebit model

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subthreshold logicRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Ultra-low power subthreshold logic with Germanium junctionless transistors

Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate

Elliptical nanowire FET: Modeling the short-channel subthreshold current caused by interface-trapped-charge and its evaluation for subthreshold logic gate

Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate

A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates

Subthreshold logic for low-area and energy efficient true random number generator

Estimation methods for static noise margins in CMOS subthreshold logic circuits

Performance Prospects of Subthreshold Logic Circuits

A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

Design and estimation of power and delay using high Vth nmos under subthreshold logic operation of SRAM onebit model

subthreshold logic
Recently Published Documents