Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors
2008 ◽
Vol 100
(4)
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pp. 042045
2008 ◽
Vol 8
(1)
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pp. 22-34
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2007 ◽
Vol 54
(9)
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pp. 2143-2154
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2009 ◽
Vol 86
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pp. 1876-1882
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2010 ◽
Vol 31
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pp. 656-658
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2011 ◽
Vol 28
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pp. 107302
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