Design of systolic array multiplier circuit using reversible logic

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) ◽

10.1109/rteict.2017.8256883 ◽

2017 ◽

Author(s):

Chinthaparthi Madhulika ◽

V. Shiva Prasad Nayak ◽

Chaluvadi Prasanth ◽

Tumma Hemanth Sai Praveen

Keyword(s):

Systolic Array ◽

Reversible Logic ◽

Array Multiplier ◽

Multiplier Circuit

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Design of array multiplier circuit using reversible logic approach with optimized performance parameters

Smart Healthcare for Disease Diagnosis and Prevention ◽

10.1016/b978-0-12-817913-0.00013-4 ◽

2020 ◽

pp. 115-123

Author(s):

Vandana Shukla ◽

O.P. Singh ◽

G.R. Mishra ◽

R.K. Tiwari

Keyword(s):

Reversible Logic ◽

Performance Parameters ◽

Array Multiplier ◽

Logic Approach ◽

Multiplier Circuit

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High Performance Array Multiplier using Reversible Logic Structure

2018 International Conference on Current Trends towards Converging Technologies (ICCTCT) ◽

10.1109/icctct.2018.8550872 ◽

2018 ◽

Author(s):

K. Yugandhar ◽

V. Ganesh Raja ◽

M. Tejkumar ◽

D. Siva

Keyword(s):

High Performance ◽

Reversible Logic ◽

Array Multiplier ◽

Logic Structure

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A 4-bit array multiplier design by reversible logic

Information Technology ◽

10.1201/b18776-3 ◽

2015 ◽

pp. 5-8

Author(s):

Junzhou Qian ◽

Junchao Wang

Keyword(s):

Reversible Logic ◽

Array Multiplier

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Systolic array multiplier for augmenting data center networks communication link

Cluster Computing ◽

10.1007/s10586-018-2092-4 ◽

2018 ◽

Vol 22 (S6) ◽

pp. 13773-13783

Author(s):

S. Subathradevi ◽

C. Vennila

Keyword(s):

Systolic Array ◽

Data Center ◽

Communication Link ◽

Data Center Networks ◽

Array Multiplier

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A 4-bit array multiplier design by reversible logic

Information Technology ◽

10.1201/b18776-5 ◽

2015 ◽

pp. 21-24

Keyword(s):

Reversible Logic ◽

Array Multiplier

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Two's-complement systolic array multiplier with applications to DSP hardware

International Journal of Electronics ◽

10.1080/00207218908925407 ◽

1989 ◽

Vol 66 (4) ◽

pp. 507-518

Author(s):

M. A. SID-AHMED

Keyword(s):

Systolic Array ◽

Array Multiplier

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PERAM: Ultra Power Efficient Array Multiplier Using Reversible Logic for High-Performance MAC

Lecture Notes in Networks and Systems - Inventive Communication and Computational Technologies ◽

10.1007/978-981-15-7345-3_64 ◽

2020 ◽

pp. 747-756

Author(s):

E. Rishi Kiran ◽

Swathi Vangala ◽

J. V. R. Ravindra

Keyword(s):

High Performance ◽

Reversible Logic ◽

Power Efficient ◽

Array Multiplier

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Scalable Systolic Array Multiplier Optimized by Sparse Matrix

10.1109/asicon52560.2021.9620326 ◽

2021 ◽

Author(s):

RiMing Jia ◽

Tu Xu ◽

YuChun Chang

Keyword(s):

Systolic Array ◽

Sparse Matrix ◽

Array Multiplier

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Performance metrics analysis of 4 bit array multiplier circuit using 2 PASCL logic

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

10.1109/icgccee.2014.6922276 ◽

2014 ◽

Author(s):

Syed Ateequr Rahman ◽

Gargi Khanna

Keyword(s):

Performance Metrics ◽

Array Multiplier ◽

Multiplier Circuit

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Voltage-multiplier circuit

AccessScience ◽

10.1036/1097-8542.735810 ◽

2015 ◽

Keyword(s):

Voltage Multiplier ◽

Multiplier Circuit

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