The Development of Frequency Tripler Based on Six-Anode Schottky Varactors

The development of a millimeter-wave unbalanced frequency tripler based on the nonlinear characteristics of planar Schottky varactors is presented. The entire module is designed by hybrid integration. A frequency multiplier circuit model was established to reflect the influence of diode parameters and the impedance matching on the multiplier in different frequency bands. The effect of junction imbalance on the output power of the frequency multiplier was investigated and the multiplier was improved based on the basic design. The addition of a cut microstrip stub in the improved diode unit reduced the impact of a power imbalance on frequency multiplier performance. The characteristics of the multiplier circuit were analyzed by the full-wave electromagnetic simulation of the three-dimensional structure and the harmonic balance simulation of the circuit. Test results showed that the peak output power of the improved frequency tripler was 12.6 mW at 277 GHz with an input power of 200 mW, an effective 12% improvement over the basic design.

Fractal mathematical over extended finite fields Fp[x]/(f(x))

In this paper, we have defined an algorithm for the construction of iterative operations, based on dimensional projections and correspondence between the properties of extended fields, with respect to modular reduction. For a field with product operations R(x) ⊗ D(x), over finite fields, GF[(pm)n−k]. With Gp[x]/(g(f(x)), whence the coefficient of the g(x) is replaced after a modular reduction operation, with characteristic p. Thus, the reduced coefficients of the generating polynomial of G contain embedded the modular reduction and thus simplify operations that contain basic finite fields. The algorithm describes the process of construction of the GF multiplier, it can start at any stage of LFSR; it is shift the sequence of operation, from this point on, thanks to the concurrent adaptation, to optimize the energy consumption of the GF iterative multiplier circuit, we can claim that this method is more efficient. From this, it was realized the mathematical formalization of the characteristics of the iterative operations on the extended finite fields has been developed, we are applying a algorithm several times over the coefficients in the smaller field and then in the extended field, concurrent form.

A Quad-Band RF Circuit for Enhancement of Energy Harvesting

Radio frequency energy harvesting is one of the new renewable sources that faces some technical challenges, which limit its performance. This study presents two scenarios to enhance the harvested power. The first scenario introduces a quad-band voltage multiplier circuit with a single receiving antenna and four band-pass filters of elliptic type. In this scenario, four frequencies of the Global System for Mobile communications, Universal Mobile Telecommunications System, and Wireless Fidelity frequency bands have been considered for the study. The second scenario proposes a quad-band voltage multiplier circuit with four receiving antennas at the same frequency bands as the first scenario. High conversion efficiencies were achieved for the two scenarios. The proposed quad-band system developed a harvested power level, sufficient for powering up low power micro-devices with no need for an external power supply.

Design and Analysis of Multiplier Using High Speed Adders

In all digital signal processing (DSP) applications like FFT, digital filters the main problem faced by processor is its propagation delay. Every high speed signal processing is depends on multiplier circuits. Multiplier performance is directly influenced by the adder design. In this paper, we design low power and high speed carry look ahead (CLA) adder for multiplier circuit by using multi value logic (MVL) based on quaternary signed digits (QSD). The ability of multi value logic (MVL) circuits to achieve more information density and high operating speed when compared to that of existing binary circuits is highly impressive. MVL circuits have attracted important attention for the design of digital systems. Based on quaternary signed digits, the carry look ahead adder is designed, implemented in multiplier circuit and simulated by using cadence virtuoso design suite by 180nF technology.

Design of folded cascode op amp and its application – bandgap reference circuit

Purpose Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design. Design/methodology/approach This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5. Findings The post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill. Research limitations/implications Slew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out. Practical implications Reference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools. Social implications BGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout. Originality/value FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

Development of mathematical model and circuit emulators for four lobe memristive behaviour

Purpose This paper aims to develop a mathematical model for four-lobe memristor (FLM) element. The four-lobe memristive behaviour can be used in realization of hyperchaotic oscillators and implementation of multi-bit memories. For verification of the developed mathematical framework, two FLM circuit emulators have been presented using VDCC and IC LM13700, respectively. Design/methodology/approach A mathematical model for FLM has been developed in which, the condition for the existence of symmetrical four lobes, instances and coordinates of the end points of lobes has been derived and presented. Using this mathematical framework, a FLM emulator based on VDCC has been developed. To validate the possibility of practical implementation of FLM concept, an IC LM13700-based circuit has also been developed. The workability of VDCC based circuit has been verified by running simulations in PSPICE environment using CMOS VDCC model. Similarly, the behaviour of LM13700 IC-based circuit has been confirmed by SPICE model of LM13700 IC. Findings It has been shown mathematically that under certain conditions, third-order flux dependent equation of memductance can be used to generate four lobes on the transient v-i plane. Also, two FLM emulators without using any voltage multiplier circuit/IC have been reported. Originality/value From the best knowledge of the authors, there are no such FLM emulators that have been reported in literature so far, which operates at practical operating frequencies.