A 4-bit array multiplier design by reversible logic

2018 ◽

Cited By ~ 1

Author(s):

K. Yugandhar ◽

V. Ganesh Raja ◽

M. Tejkumar ◽

D. Siva

Keyword(s):

High Performance ◽

Reversible Logic ◽

Array Multiplier ◽

Logic Structure

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A 4-bit array multiplier design by reversible logic

Information Technology ◽

10.1201/b18776-3 ◽

2015 ◽

pp. 5-8

Author(s):

Junzhou Qian ◽

Junchao Wang

Keyword(s):

Reversible Logic ◽

Array Multiplier

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PERAM: Ultra Power Efficient Array Multiplier Using Reversible Logic for High-Performance MAC

Lecture Notes in Networks and Systems - Inventive Communication and Computational Technologies ◽

10.1007/978-981-15-7345-3_64 ◽

2020 ◽

pp. 747-756

Author(s):

E. Rishi Kiran ◽

Swathi Vangala ◽

J. V. R. Ravindra

Keyword(s):

High Performance ◽

Reversible Logic ◽

Power Efficient ◽

Array Multiplier

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Design of array multiplier circuit using reversible logic approach with optimized performance parameters

Smart Healthcare for Disease Diagnosis and Prevention ◽

10.1016/b978-0-12-817913-0.00013-4 ◽

2020 ◽

pp. 115-123

Author(s):

Vandana Shukla ◽

O.P. Singh ◽

G.R. Mishra ◽

R.K. Tiwari

Keyword(s):

Reversible Logic ◽

Performance Parameters ◽

Array Multiplier ◽

Logic Approach ◽

Multiplier Circuit

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Design of systolic array multiplier circuit using reversible logic

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) ◽

10.1109/rteict.2017.8256883 ◽

2017 ◽

Cited By ~ 1

Author(s):

Chinthaparthi Madhulika ◽

V. Shiva Prasad Nayak ◽

Chaluvadi Prasanth ◽

Tumma Hemanth Sai Praveen

Keyword(s):

Systolic Array ◽

Reversible Logic ◽

Array Multiplier ◽

Multiplier Circuit

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Quaternary reversible logic synthesis based on GF(4) Shannon expansion

Advanced Computer Control ◽

10.2495/icacc130171 ◽

2014 ◽

Author(s):

Lu Cangang ◽

Guan Zhijin ◽

He Jinfeng

Keyword(s):

Logic Synthesis ◽

Reversible Logic ◽

Reversible Logic Synthesis

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HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.7.1.15530 ◽

2019 ◽

Vol 7 (1) ◽

pp. 24

Author(s):

N. SURESH ◽

K. S. SHAJI ◽

KISHORE REDDY M. CHAITANYA ◽

◽

...

Keyword(s):

Low Power ◽

High Speed ◽

Array Multiplier

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FPGA Implementation of Image Cryptology using Reversible Logic Gates

International Journal of Advanced Trends in Computer Science and Engineering ◽

10.30534/ijatcse/2020/06932020 ◽

2020 ◽

Vol 9 (3) ◽

pp. 2522-2526

Author(s):

Murali Krishna B

Keyword(s):

Logic Gates ◽

Reversible Logic ◽

Fpga Implementation ◽

Reversible Logic Gates

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Algorithm of Optimizing Quantum Reversible Logic Synthesis

Journal of Software ◽

10.3724/sp.j.1001.2009.03407 ◽

2009 ◽

Vol 20 (9) ◽

pp. 2332-2343

Author(s):

Zhi-Qiang LI ◽

Wen-Qian LI ◽

Han-Wu CHEN

Keyword(s):

Logic Synthesis ◽

Reversible Logic ◽

Reversible Logic Synthesis

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Implementation of Reversible Logic Gates with Quantum Gates

2021 IEEE 11th Annual Computing and Communication Workshop and Conference (CCWC) ◽

10.1109/ccwc51732.2021.9376060 ◽

2021 ◽

Author(s):

Mummadi Swathi ◽

Bhawana Rudra

Keyword(s):

Logic Gates ◽

Reversible Logic ◽

Quantum Gates ◽

Reversible Logic Gates

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A 4-bit array multiplier design by reversible logic

High Performance Array Multiplier using Reversible Logic Structure

A 4-bit array multiplier design by reversible logic

PERAM: Ultra Power Efficient Array Multiplier Using Reversible Logic for High-Performance MAC

Design of array multiplier circuit using reversible logic approach with optimized performance parameters

Design of systolic array multiplier circuit using reversible logic

Quaternary reversible logic synthesis based on GF(4) Shannon expansion

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

FPGA Implementation of Image Cryptology using Reversible Logic Gates

Algorithm of Optimizing Quantum Reversible Logic Synthesis

Implementation of Reversible Logic Gates with Quantum Gates

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