Notice of Violation of IEEE Publication Principles0.13μm CMOS DBS demodulator front-end using a 250MS/s 8 bit time interleaved pipeline ADC and a sampled loop filter PLL

2008 ◽  
Author(s):  
A. Maxim ◽  
R. Poorfard ◽  
M. Chennam
Keyword(s):  
Pipeline Adc ◽  
Loop Filter ◽  
Front End ◽  
Time Interleaved

Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

2013 ◽  
Vol 473 ◽  
pp. 50-53
Author(s):  
Jie Lin ◽  
Fei Yan Mu
Keyword(s):  
Dynamic Range ◽  
Harmonic Distortion ◽  
High Accuracy ◽  
Pipeline Adc ◽  
Nonlinearity Error ◽  
Front End ◽  
Sample And Hold ◽  
Spurious Free Dynamic Range ◽  
Bicmos Process ◽  
Free Dynamic

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.

A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC

2013 ◽  
Author(s):  
Manar El-Chammas ◽  
Xiaopeng Li ◽  
Shigenobu Kimura ◽  
Kenneth Maclean ◽  
Jake Hu ◽  
...  
Keyword(s):  
Pipeline Adc ◽  
Time Interleaved

scholarly journals An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H

2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Wilmar Carvajal ◽  
Wilhelmus Van Noije
Keyword(s):  
Analog Circuits ◽  
Bottom Plate ◽  
Pipeline Adc ◽  
Digital Correction ◽  
Fully Differential ◽  
Reconfigurable Design ◽  
Parallel Pipeline ◽  
Block Level ◽  
Differential Circuits ◽  
Time Interleaved

This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12 mW while sampling a 500 kHz input signal. Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 μm AMS technology, and some postlayout results are shown.

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