Low voltage low power current mode analog to digital converter flash

Author(s):  
Mounira Bchir ◽  
Nejib Hassen ◽  
Thouraya Ettaghzout ◽  
Kamel Besbes
2019 ◽  
Vol 15 (4) ◽  
pp. 368-378 ◽  
Author(s):  
Mounira Bchir ◽  
Thouraya Ettaghzouti ◽  
Néjib Hassen

This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversion frequency (350 MHz) and low power consumption that is 2.76 mW.


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