A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems

“In this paper FPGA based hardware co-simulation of an area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with look up table (LUT) accesses. Parallel Distributed arithmetic (PDA) look up table approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA using VHDL. The proposed design is hardware co-simulated using System Generator10.1, synthesized with Xilinx ISE 10.1 software, and implemented on Virtex-4 based xc4vlx25-10ff668 target device. Results show that the proposed design operates at 17.5 MHz throughput and consumes 0.468W power with considerable reduction in required resources to implement the design as compared to Coregen and add/shift based design styles. Due to this reduction in required resources the proposed design can also be implemented on Spartan-3 FPGA device to provide cost effective solution for DSP and wireless communication applications.”

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Implementation of an efficient two-step SOVA turbo decoder for wireless communication systems

GLOBECOM '05. IEEE Global Telecommunications Conference, 2005. ◽

10.1109/glocom.2005.1578179 ◽

2005 ◽

Cited By ~ 5

Author(s):

J.H. Han ◽

A.T. Erdogan ◽

T. Arslan

Keyword(s):

Wireless Communication ◽

Communication Systems ◽

Wireless Communication Systems ◽

Turbo Decoder

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Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

Entropy ◽

10.3390/e21080814 ◽

2019 ◽

Vol 21 (8) ◽

pp. 814

Author(s):

Jun Li ◽

Xiumin Wang ◽

Jinlong He ◽

Chen Su ◽

Liang Shan

Keyword(s):

Wireless Communication ◽

Communication Systems ◽

Lookup Table ◽

Clock Frequency ◽

High Complexity ◽

Decoding Algorithm ◽

Turbo Decoder ◽

Map Algorithm ◽

Map Decoding ◽

Log Map

Turbo codes have been widely used in wireless communication systems due to their good error correction performance. Under time division long term evolution (TD-LTE) of the 3rd generation partnership project (3GPP) wireless communication standard, a Log maximum a posteriori (Log-MAP) decoding algorithm with high complexity is usually approximated as a lookup-table Log-MAP (LUT-Log-MAP) algorithm and Max-Log-MAP algorithm, but these two algorithms have high complexity and high bit error rate, respectively. In this paper, we propose a normalized Log-MAP (Nor-Log-MAP) decoding algorithm in which the function max* is approximated by using a fixed normalized factor multiplied by the max function. Combining a Nor-Log-MAP algorithm with a LUT-Log-MAP algorithm creates a new kind of LUT-Nor-Log-MAP algorithm. Compared with the LUT-Log-MAP algorithm, the decoding performance of the LUT-Nor-Log-MAP algorithm is close to that of the LUT-Log-MAP algorithm. Based on the decoding method of the Nor-Log-MAP algorithm, we also put forward a normalization functional unit (NFU) for a soft-input soft-output (SISO) decoder computing unit. The simulation results show that the LUT-Nor-Log-MAP algorithm can save about 2.1% of logic resources compared with the LUT-Log-MAP algorithm. Compared with the Max-Log-MAP algorithm, the LUT-Nor-Log-MAP algorithm shows a gain of 0.25~0.5 dB in decoding performance. Using the Cyclone IV platform, the designed Turbo decoder can achieve a throughput of 36 Mbit/s under a maximum clock frequency of 44 MHz.

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