scholarly journals FPGA Based Hardware Co-Simulation of an Area and Power Efficient FIR Filter for Wireless Communication Systems

2010 ◽  
Vol 1 (1) ◽  
pp. 113-122
Author(s):  
Rajesh Kumar ◽  
Swapna Devi ◽  
S.S. Pattnaik
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Cost Effective ◽  
Fir Filter ◽  
Wireless Communication Systems ◽  
Effective Solution ◽  
Distributed Arithmetic ◽  
Power Efficient ◽  
Look Up Table ◽  
The Look

“In this paper FPGA based hardware co-simulation of an area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with look up table (LUT) accesses. Parallel Distributed arithmetic (PDA) look up table approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA using VHDL. The proposed design is hardware co-simulated using System Generator10.1, synthesized with Xilinx ISE 10.1 software, and implemented on Virtex-4 based xc4vlx25-10ff668 target device. Results show that the proposed design operates at 17.5 MHz throughput and consumes 0.468W power with considerable reduction in required resources to implement the design as compared to Coregen and add/shift based design styles. Due to this reduction in required resources the proposed design can also be implemented on Spartan-3 FPGA device to provide cost effective solution for DSP and wireless communication applications.”

VLSI Design and Comparison of DA and LMS Based Reconfigurable FIR Filter

2016 ◽  
Vol 5 (2) ◽  
pp. 124
Author(s):  
P. Hemanthkumar ◽  
Y. Sai Kiran ◽  
V. Nava Teja
Keyword(s):  
Performance Metrics ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Fir Filter ◽  
Inner Product ◽  
Distributed Arithmetic ◽  
Power Efficient ◽  
Consumption Energy ◽  
The Look ◽  
Suitable Area

<p>Here, we exhibit the design optimization of one- and two-dimensional fully-pipelined computing structures for area-delay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. This plan is found to offer a flexible choice of the address length of the look-up-tables (LUT) for DA-based computation to determine suitable area-time trade-off. It is seen that by using smaller address-lengths for DA-based computing units, it is possible to decrease the memory-size but on the other side that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density and energy throughput are estimated for different filter orders and address-lengths. Obtained results on analysis shows that performance metrics of the proposed implementation is broadly in line with theoretical expectations. We have seen that the choice of address-length M=4 gives the best of area-delay power-efficient realizations of the FIR filter for different filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.</p>

scholarly journals Dual-Band Half Psi Shaped Antenna for WLAN, Wi-Fi and WiMAX Applications

2019 ◽  
Vol 8 (6) ◽  
pp. 1385-1388
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Impedance Matching ◽  
Ground Surface ◽  
Cost Effective ◽  
Dual Band ◽  
Wireless Communication Systems ◽  
Feed Line ◽  
Dual Band Antennas ◽  
The Cost

In the last few decades, the evolution in new-fashioned wireless communication systems has actuated augmented exploration on uncomplicated dual band antennas. In this paper, a dual-band half psi shaped antenna for WLAN, Wi-Fi and WiMAX appliances is designed and analyzed. The intended antenna constitutes a half psi shaped radiating patch on the cost effective FR4-substrate with 1.6 mm thickness. A 50 ohms feed line is employed to feed half psi shaped antenna. Here a preferable impedance matching is attained by truncating a portion of the ground surface. The intended antenna has the potential to resonate between the frequency bands of 1.88 GHz-2.75 GHz and 5.17 GHz-5.74 GHz with S11 below -10 dB. The design of the antenna and its behavior over various frequencies ranges is done with the use of HFSS. The proposed antenna has higher gains at two regions. The simulated antenna is also prototyped and a fine similarity is attained in between the simulated parameters and measured parameters.

scholarly journals Design Methods for Reconfigurable Filters: A Review

2019 ◽  
Vol 5 (1) ◽  
Author(s):  
Sunil Raosaheb Gagare . ◽  
Dolly Reney .
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Filter Design ◽  
Cost Effective ◽  
Design Methods ◽  
Microwave Filters ◽  
Wireless Communication Systems ◽  
Compact Size ◽  
Electrical Components ◽  
Reconfigurable Filters

The new design methods of microwave filter has proved its significance for use in wireless communication systems. Modern wireless communication systems require microwave filters to have stringent specifications such as compact size, robust, conformal, light weight and more importantly cost effective while maintaining its electrical characteristics. Micro-strip filter design and reconfigurable filters present a better prospectus in this regards as it meets the specifications of modern wireless communication applications. Reconfigurable filters can provide control over parameters such as frequency, bandwidth and selectivity while reducing the need of number of switches sandwiched between electrical components. Different methods have provided a new dimension for designing microwave filters .In this article, we present a review on design methods for reconfigurable band-pass filters for next generation wireless technologies such as 4G, 5G and IOT.

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