Petri Net Based CTL Model Checking: Using a New Method to Construct OBDD Variable Order

Author(s):  
Leifeng He ◽  
Guanjun Liu
2015 ◽  
Vol 742 ◽  
pp. 330-334
Author(s):  
Chun Jian Wang ◽  
Wei Yue ◽  
Hai Yan Ji

In allusion to the need of analyzing complex system, we have proposed a method named multi-grade color Petri net. We for the first time use this new method to analyze a missile training simulator system. This model can accurately reflect the complex environments of the system and avoid the difficulty occurring often in developing accurate mathematics model by using classical research approach.


2012 ◽  
Vol 605-607 ◽  
pp. 336-340
Author(s):  
Hou Xing You

In the whole life cycle of production process, the stability of production manufacturing system is an important production factor. However, there were a few researches about the system stability in the past years. In this paper, for the stability of production manufacturing system, a new method is proposed based on Petri-net and analytic hierarchy process. In the proposed method, the reachability of manufacturing system is judged by using Petri-net, and the system stability is calculated by the successful probability of the key production nodes. Finally, evaluation steps of the new method are given, and the new evaluation method is applied in case study.


2006 ◽  
Vol 11 (5) ◽  
pp. 1297-1301 ◽  
Author(s):  
Zhou Conghua ◽  
Chen Zhenyu

2012 ◽  
Vol 58 (4) ◽  
pp. 403-410 ◽  
Author(s):  
Arkadiusz Bukowiec ◽  
Marian Adamski

Abstract In this paper a new method of Petri net array-based synthesis is proposed. The method is based on decomposition of colored interpreted macro Petri net into state machine subnets. Each state machine subnet is determined by one color. During the decomposition process macroplaces are expanded or replaced by doublers of macroplace. Such decomposition leads to parallel implementation of a digital system. The structured encoding of places is done by using minimal numbers of bits. Colored microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs


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