A 19 W, 50 kS/s, 0.008-400V/s Cyclic Voltammetry Readout Interface with a Current Feedback Loop and On-Chip Pattern Generation

Author(s):  
Shao-Yung Lu ◽  
Yu-Te Liao
Biomag 96 ◽  
2000 ◽  
pp. 126-129
Author(s):  
A. V. Shabalin ◽  
N. V. Golyshev ◽  
S. V. Motorin ◽  
B. M. Rogatchevskij

2020 ◽  
Vol 10 (23) ◽  
pp. 8478
Author(s):  
Donggeun You ◽  
Hyunwoo Heo ◽  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Sangmin Lee ◽  
...  

This paper presents a power line interference (PLI) reduction technique with a current-reused current-feedback instrumentation amplifier (CFIA) for electrocardiogram (ECG) recording. In a portable two-electrode ECG monitoring application, the presence of undesired PLI may severely corrupt the quality of ECG recording. Since PLI can be over a few volts, the input signal including the ECG signal can exceed the supply or ground level by an electrostatic discharge (ESD) diode in input/output (I/O) pad. To prevent this problem, this paper presents a continuous-time input common-mode current feedback loop that can limit displacement current from a capacitive coupling between the human body and a power line. The continuous-time input common-mode current feedback loop can clamp an input common-mode voltage to the saturation region of the input transistor of the current-reused CFIA. After the clamping procedure, the clamped input signal is amplified by the current-reused CFIA. The proposed circuit was designed using a 0.18-μm bipolar-complementary metal semiconductor–double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 1.8 mm2. The total power consumption is 18 μW with 1.8 V. The input-referred noise and noise efficiency factor (NEF) of the current-reused CFIA is 2.68 μVRMS and 4.28 with 107 Hz, respectively.


J3eA ◽  
2021 ◽  
Vol 20 ◽  
pp. 0001
Author(s):  
Romain Delpoux ◽  
Lubin Kerhuel ◽  
Vincent Léchappé

This paper proposes a method for Rapid Control Prototyping (RCP) targeting microcontrollers. The methodology relies on a Matlab/Simulink interface which makes the target configuration and coding easier. Developing low level embedded code is bypassed by a high-level implementation which is straightforward for control system engineers. This article is intended for students, engineers or researchers looking to validate the effectiveness of their control algorithms on industrial targets. The design procedure is illustrated by testing various speed and current feedback loop on a DC motor.


Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.


Author(s):  
Kazuki Monta ◽  
Leonidas Kataselas ◽  
Ferenc Fodor ◽  
Alkis Hatzopoulos ◽  
Makoto Nagata ◽  
...  
Keyword(s):  
Ir Drop ◽  

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