Cost-effective flow table designs for high-speed routers: architecture and performance evaluation

2002 ◽  
Vol 37 (9) ◽  
pp. 1089-1099 ◽  
Author(s):  
Jun Xu ◽  
M. Singhal
Author(s):  
A Chakravarty ◽  
R S Menon ◽  
M Goyal ◽  
N Ahmed ◽  
M Jadhav ◽  
...  

2011 ◽  
Vol 233-235 ◽  
pp. 298-301
Author(s):  
Qi Cheng Liu ◽  
Yong Jian Liu

Oil component and molecule structures is studied by application of gas chromatogram, infrared spectrum and nuclear magnetic resonance to develop high efficiency and cost effective surfactant used for chemical flooding, HZS surfactant has been developed on basis of relationship between effectiveness and structure of the surfactant. Study on surfactant structure characterization and performance evaluation suggests that oil/water interfacial tension is super low when distribution of carbon number of main component of surfactant is identical to the distribution of main component of oil, and concentration impairment due to surfactant retention on surface of core. Reference can be provided to reservoir selection and surfactant development of other oilfield.


RSC Advances ◽  
2020 ◽  
Vol 10 (73) ◽  
pp. 44747-44755
Author(s):  
V. S. Vendamani ◽  
S. V. S. Nageswara Rao ◽  
A. P. Pathak ◽  
Venugopal Rao Soma

We report the fabrication and performance evaluation of cost-effective, reproducible silver nanodendrite (AgND) substrates, possessing high-density trunks and branches, achieved by a simple electroless etching and used for the trace detection of RDX and Ammonium Nitrate.


Author(s):  
Mahadevan Suryakumar ◽  
Lu-Vong T. Phan ◽  
Mathew Ma ◽  
Wajahat Ahmed

The alarming growth of power increase has presented numerous packaging challenges for high performance processors. The average power consumed by a processor is the sum of dynamic and leakage power. The dynamic power is proportional to V^2, while the leakage current (therefore leakage power) is proportional to V^b where V is the voltage and b>1 for modern processes. This means lowering voltage reduces energy consumed per clock cycle but reduces the maximum frequency at which the processor can operate at. Since reducing voltage reduces power faster than it does frequency, integrating more cores into the processor would result in better performance/power efficiency but would generate more memory accesses, driving a need for larger cache and high speed signaling [1]. In addition, the design goal to create unified package pinout for both single core and multicore product flavors adds additional constraint to create a cost effective package solution for both market segments. This paper discusses the design strategy and performance of dual die package to optimize package performance for cost.


Sign in / Sign up

Export Citation Format

Share Document