Thermal Management for Chip-Scale Atomic Clocks

Power dissipation of chip-scale atomic clocks is one of the major design considerations. The largest power dissipation is for temperature control of the vertical-cavity surface-emitting laser (VCSEL) and cesium vapor cell. For example, the temperature of the VCSEL and Cs cell have to both be at 70±0.1°C or there will be frequency shift which will ruin the lock of the clock. These temperatures have to be maintained even under a large temperature variation such as −40°C to 50°C. There are three major thermal designs to consider: a) micro-heaters to fine-tune the temperatures of VCSEL and Cs cell, b) use of waste heat from other units to heat the system when outside temperature is low, and c) use of a thermal switch to release any extra waste heat when ambient temperatures are high. These three thermal designs have been incorporated in to a thermal test vehicle, which will be used to develop a thermal management design for the clock. This paper describes the proposed clock design, creation of the thermal test vehicle and development of a bimetallic snap based thermal conduction switch. The switch has been demonstrated to change thermal resistance from 52.9±2.8 K/W when the switch is open to 19.5±1.1 K/W with the switch closed.

Empirical Optimization of High Density Plate-Fin Heat Sink for Constant Pumping Power in Low Profile Cooling Application

Since the VLSI processors are increasing power in accordance with exponential law, cooling solutions for such as personal computers have been evolving for over a decade. Recent heat sinks are designed with high dense fins and low profile to adapt to a high heat flux source within a slim enclosure. To achieve such compact cooling solution, thin fin and small gap is desirable. In addition, the pumping power is also limited by the allowable narrow space for fans. Thus it is important to minimize the thermal resistance for given pumping power that we define the optimum. Due to the lack of literatures on topic of low profile and high dense fins experiments, an apparatus was specially built to measure the thermal and fluid dynamic performance at the same time. Since such a high dense fin arrangement requires extra space on the sides by manufacturing reasons, the impact of bypass flow needs to be considered. The experiments are carefully carried out and the results are precisely compared with numerical analysis. The numerical model aiming to find the optimum for given pumping power is discussed with extrapolating the data points. This report is concluded with the best configuration of plate fins of low profile heat sinks for a given fan performance.

The Impact of Varying Feature Dimensions on Substrate Reliability Risks

A sensitivity study is undertaken to characterize the impact of varying feature dimensions in emerging electronic packaging technologies. Specifically, the overall structural performance of the substrate under use conditions (thermal and combined thermomechanical loading) is investigated. The study consists of both modeling and experimental efforts. Modeling approaches are employed within the framework of a finite element code to simulate performance of different design geometry combinations in the known failure mode of solder resist layer cracking. In the models, two levels of complexity are used to better identify the impact of the individual features on the overall substrate reliability. First, local geometry is captured by including each substrate layer. Individual component geometries like microvias and PTHS are also explicitly modeled to capture synergistic failures modes. Second, more realistic non-linear material properties are used to characterize time, temperature, and rate-dependant constitutive behavior of individual substrate materials such as buildup, core, metal, etc. In the experiments, substrate warpage and reliability data is collected for validating the predictive modeling capability. From this study, directions for future design guidelines varying feature dimensions while maintaining substrate reliability are proposed.

Prediction of Microelectronic Substrate Warpage Using Homogenized Thermomechanical Finite Element Models

High-density microelectronic substrates, used in organic CPU packages, are comprised of several polymer, fiber-weave, and copper layers and are filled with a variety of complex features such as traces, micro-vias, Plated-Through-Holes (PTH), and adhesion holes. When subjected to temperature changes, these substrates may warp, driven by the mismatch in Coefficients of Thermal Expansion (CTE) of the constituent materials. This study focused on predicting substrate warpage in an isothermal condition. The numerical approach consisted of three major steps: estimating homogenized (effective) thermomechanical properties of the features; calculating effective properties of discretized layers using the effective properties of the features; and assembling the layers to create 2D Finite Element (FE) plate models and to calculate warpage of the whole substrates. The effective properties of the features were extracted from 3D unit cell FE models, and closed-form approximate expressions were developed using the numerical results, curve fitting, and some simple bounds. The numerical approach was applied to predict warpage of production substrates, analyzed, and validated against experimentally measured stiffness and CTEs. In this paper, the homogenization approach, numerical predictions, and experimental validation are discussed.

A Thermo-Viscoelastic Analysis and Reliability Evaluation for a Single-Sided CSP

In the present paper, a reliability of a single-sided chip-size package (CSP) manufactured using a non-conductive adhesive stud bump direct interconnection method is investigated. The reliability of the CSP is closely related with normal stress between an IC chip and a gold bump. Total normal stress can be decomposed into two parts, deflection related and thermal expansion related. The deflection for a three-layered plate, which is taken into account viscoelastic properties for the resin-sealed sheet and the substrate, respectively, is calculated and compared with experimental results on the deflection of the single-sided CSP. A relationship between the normal stress and the curvature derived from deflection is deduced. Through the use of this relationship, the variation of normal stress with the heat cycle is obtained considering the viscoelastic properties of materials. Furthermore, a relaxation behavior for the thermal stress in the resin-sealed sheet between two rigid walls considering its viscoelastic property is investigated. Summing up normal stresses for each calculation yields the normal stress between the IC and the bump. A relationship between the normal stress and the life of single-sided CSP is investigated for heat cycle. The life in experiment can be explained by the relaxation in the normal stress and the amplitude of the normal stress.

Thermal and Mechanical Properties of Silicone Thermal Interface Materials With Varying Cross-Link Densities

Thermal Interface Materials (TIMs) play a key role in the thermal management of microelectronics by providing a path of low thermal impedance between the heat generating devices and the heat dissipating components (heat spreader/sink). In addition, TIMs need to reliably maintain this low thermal resistance path throughout the operating life of the device. Currently, several different TIM material solutions are employed to dissipate heat away from semiconductor devices. Thermal greases, adhesives, gels, pads, and phase change materials are among these material solutions. Each material system has its own advantages and associated application space. While thermal greases offer excellent thermal performance, their uncured state makes them susceptible to pump-out and other degradation mechanisms. On the other hand, adhesives offer structural support but offer a higher heat resistance path. Gels are designed to provide a level of cross-linking to allow the thermal performance of greases and prevent premature degradation. However, the degree of crosslinking can have a significant effect of the behavior of gels. In this research, TIMs with varying cross-linking densities are studied and their thermal and mechanical properties reported. The base resin systems and fillers were maintained constant, while slight compositional alternations were made to induce different degrees of cross-linking.

Reliability and Characterization of Micro-Packages in a Wafer Level Au-Si Eutectic Vacuum Bonding Process

A Au-Si eutectic vacuum packaging process was evaluated using high sensitivity poly-Si Pirani vacuum sensors. Encapsulation of devices was achieved by bonding a silicon cap wafer to a device wafer using a Au-Si eutectic solder at above 390°C in a vacuum bonder. The Au-Si eutectic solder encircled the devices, providing an airtight seal. The Pirani gauges were encapsulated and tested over a period of several months in order to determine base pressures and leak/outgassing rates of the micro-cavities. Packaged devices without getters showed initial pressures from 2 to 12 Torr with initial leak/outgassing rates of −0.073 to 80 Torr/year. Using getters, pressures as low as 5 mTorr have been achieved with leak/outgassing rates of <10 mTorr/year. Trends in pressure over time seem to indicate outgassing (desorption of atoms from inside of the microcavity) as the primary mechanism for pressure change over time.

Experimental Investigation of the Miniature Loop Heat Pipe With Flat Evaporator

Loop heat pipe (LHP) is a very versatile heat transfer device that uses capillary forces developed in the wick structure and latent heat of evaporation of the working fluid to carry high heat loads over considerable distances. Robust behaviour and temperature control capabilities of this device has enable it to score an edge over the traditional heat pipes. In the past, LHPs has been invariably assessed for electronic cooling at large scale. As the size of the thermal footprint and available space is going down drastically, miniature size of the LHP has to be developed. In this paper, results of the investigation on the miniature LHP (mLHP) for thermal control of electronic devices with heat dissipation capacity of up to 70 W have been discussed. Copper mLHP with disk-shaped flat evaporator 30 mm in diameter and 10 mm thickness was developed. Flat evaporators are easy to attach to the heat source without any need of cylinder-plane-reducer saddle that creates additional thermal resistance in the case of cylindrical evaporators. Wick structure made from sintered nickel powder with pore size of 3–5 μm was able to provide adequate capillary forces for the continuos circulation of the working fluid, and successfully transport heat load at the required distance of 60 mm. Heat was transferred using 3 mm ID copper tube with vapour and liquid lines of 60 mm and 200 mm length respectively. mLHP showed very reliable start up at different heat loads and was able to achieve steady state without any symptoms of wick dry-out. Tests were conducted on the mLHP with evaporator and condenser at the same level. Total thermal resistance, R total of the mLHP came out to be in the range of 1–4°C/W. It is concluded from the outcomes of the investigation that mLHP with flat evaporator can be effectively used for the thermal control of the electronic equipments with restricted space and high heat flux chipsets.

Thermal Resistance of Bond-Lines Formed With Composite Thermal Interface Materials

Measurements and modeling of the thermal resistance of thin (< 100 microns) bond-lines are reported for composite thermal interface materials (TIMs). The composite TIMs consist of alumina particles dispersed in a polymer matrix to form six different adhesive materials. These model TIMs have a common matrix material and are distinguished by their particle size distributions. Bond-lines are formed in a three-layer assembly consisting of a substrate-TIM-substrate structure. The thermal resistance of the bond-line is measured, as a function of bond-line thickness, using the laser flash-technique. A linear variation of resistance with bond-line thickness is observed; Rbl = β · Lbl + Ro. A model is presented that predicts the effective thermal conductivity of the composite as a function of the particle and matrix conductivity, the particle-matrix surface conductance, the particle volume fraction and the particle size distribution. Specifically a method is introduced to account for a broad, continuous size distribution. A particle-matrix surface conductance value of ∼10W/mm2K is found to give good agreement between the measured and predicted effective thermal conductivity values of the composite TIMs.

Effect of Microstructural Characteristics of Electroless Nickel Metallisation on Solderability to Pb-Free Solder Alloys

This paper aims to gain an insight into the correlation between the microstructure and surface composition of electroless Ni-P and its behaviour during soldering with Pb free alloys including Sn-3.8Ag-0.7Cu, Sn-3.5Ag and Sn-0.7Cu. Ni-P coatings with different P contents were produced through an industrial process on copper metal substrates. The surface morphology of these coatings was observed by Scanning Electron Microscopy (SEM) and the bulk composition was analyzed by means of Energy Dispersive X-ray analysis (EDX). The mechanical properties of the coatings were evaluated by nano-indentation testing under different maximum loads. However, to understand the behaviour of P in Ni-P coatings and deterioration of the coating surfaces during exposure to air, the surfaces of the coatings were also characterised by X-ray Photoelectron Spectroscopy (XPS) for storage at different temperatures. The dependence of the solderability of Ni-P coatings on the storage time and temperature was investigated by wetting balance testing, using an inactive or active flux with or without an inert N2 atmosphere. Finally, the solderability of Ni-P coatings to Pb free solders is correlated with their composition and microstructure (e.g. surface characteristics).