Optimization of Data Center Room Layout to Minimize Rack Inlet Air Temperature

In a typical raised floor data center with alternating hot and cold aisles, air enters the front of each rack over the entire height of the rack. Since the heat loads of data processing equipment continues to increase at a rapid rate, it is a challenge to maintain the temperature within the requirements as stated for all the racks within the data center. A facility manager has discretion in deciding the data center room layout, but a wrong decision will eventually lead to equipment failure. There are many complex decisions to be made early in the design as the data center evolves. Challenges occur such as optimizing the raised floor plenum, floor tile placement, minimizing the data center local hot spots etc. These adjustments in configuration affects rack inlet air temperatures which is one of the important key to effective thermal management. In this paper, a raised floor data center with 4.5 kW racks is considered. There are four rows of racks with alternating hot and cold aisle arrangement. Each row has six racks installed. Two CRAC units supply chilled air to the data center through the pressurized plenum. Effect of plenum depth, floor tile placement and ceiling height on the rack inlet air temperature is discussed. Plots will be presented over the defined range. Now a multi-variable approach to optimize data center room layout to minimize the rack inlet air temperature is proposed. Significant improvement over the initial model is shown by using multi-variable design optimization approach. The results of multi-variable design optimization are used to present guidelines for optimal data center performance.

Comparing Shock, Random and Sine Vibration Loads of the Electronic Equipment

It is a challenge to correlate different dynamic loads. Often, attempts are made to compare the peak acceleration of sine wave to the root mean square (RMS) acceleration of random vibration and shock. However, peak sine acceleration is the maximum acceleration at one frequency. Random RMS is the square root of the area under a spectral density curve. These are not equivalent. This paper is to discuss a mathematical method to compare different kinds of dynamic damage at the resonant point of the related electronic equipment. The electronic equipment will vibrate at its resonance point when there are dynamic excitations. The alternative excitation at the resonant frequency causes the most damage. This paper uses this theory to develop a method to correlate different dynamic load conditions for electronic equipment. The theory is that if one kind of dynamic load causes the same levels of damaging effects as the other, the levels of vibration can then be related.

Characterization of Maximum Current Capacity for Microprocessor Sockets

This paper presents the current-carrying-capacity (CCC) characterization of a land-grid-array type microprocessor socket. This CCC study has been performed using both computational modeling and experiments using infrared camera. A subsequent risk assessment was performed against the maximum allowed temperature at the point of pressure contact of socket pin for the use-condition socket pin current and motherboard temperature. The results from the modeling and the experimental results are compared.

Effect of Microstructural Characteristics of Electroless Nickel Metallisation on Solderability to Pb-Free Solder Alloys

This paper aims to gain an insight into the correlation between the microstructure and surface composition of electroless Ni-P and its behaviour during soldering with Pb free alloys including Sn-3.8Ag-0.7Cu, Sn-3.5Ag and Sn-0.7Cu. Ni-P coatings with different P contents were produced through an industrial process on copper metal substrates. The surface morphology of these coatings was observed by Scanning Electron Microscopy (SEM) and the bulk composition was analyzed by means of Energy Dispersive X-ray analysis (EDX). The mechanical properties of the coatings were evaluated by nano-indentation testing under different maximum loads. However, to understand the behaviour of P in Ni-P coatings and deterioration of the coating surfaces during exposure to air, the surfaces of the coatings were also characterised by X-ray Photoelectron Spectroscopy (XPS) for storage at different temperatures. The dependence of the solderability of Ni-P coatings on the storage time and temperature was investigated by wetting balance testing, using an inactive or active flux with or without an inert N2 atmosphere. Finally, the solderability of Ni-P coatings to Pb free solders is correlated with their composition and microstructure (e.g. surface characteristics).

Determination of the Anand Viscoplasticity Model Constants for SnAgCu

The major focus of this work was the determination of the nine constants required for Anand’s viscoplastic constitutive model for a lead-free solder alloy, 95.5Sn3.8Ag0.7Cu and to compare them with those for SnPb. The test specimen was a cast dog bone shape based on ASTM E 8M-01, with a diameter of 4mm and a gauge length of 20mm. A series of tensile experiments were carried out: constant displacement tests ranging from 6.5 × 10−5/s to 1.0 × 10−3/s at temperatures of 20°C, 75°C, and 125°C; constant load tests at a range of loads from 10MPa to 65MPa, also at temperatures of 20°C, 75°C, and 125°C. A series of non-linear fitting processes was used to determine the model constants. Comparisons were then made with experimental measurements of the stress-plastic strain curves from constant displacement rate tests: it was found that the model matched the experimental data at low strain rates but did not capture the strain hardening effect, especially at high strain rates. A finite element model of the test was also constructed using ANSYS software. This software includes the Anand model as an option for its range of viscoplastic elements, requiring that the nine constants be input. In this case, an 8-noded axisymmetric element (VISCO108) was used to model the test specimen under constant displacement rate loading. The model was then used to predict the stress-plastic strain curve and this was compared to both the experimental measurements and the fitted Anand model. Reasonable agreement was found between the Anand model and the FE predictions at small strain rates. Finally, a BGA device was simulated under accelerated temperature cycling conditions using ANSYS with the fitted Anand for the SnAgCu solder joints. A Morrow-type fatigue life model was applied using empirical constants from two published sources and good agreement was found between experiment and predicted fatigue life.

Thermal Management for Chip-Scale Atomic Clocks

Power dissipation of chip-scale atomic clocks is one of the major design considerations. The largest power dissipation is for temperature control of the vertical-cavity surface-emitting laser (VCSEL) and cesium vapor cell. For example, the temperature of the VCSEL and Cs cell have to both be at 70±0.1°C or there will be frequency shift which will ruin the lock of the clock. These temperatures have to be maintained even under a large temperature variation such as −40°C to 50°C. There are three major thermal designs to consider: a) micro-heaters to fine-tune the temperatures of VCSEL and Cs cell, b) use of waste heat from other units to heat the system when outside temperature is low, and c) use of a thermal switch to release any extra waste heat when ambient temperatures are high. These three thermal designs have been incorporated in to a thermal test vehicle, which will be used to develop a thermal management design for the clock. This paper describes the proposed clock design, creation of the thermal test vehicle and development of a bimetallic snap based thermal conduction switch. The switch has been demonstrated to change thermal resistance from 52.9±2.8 K/W when the switch is open to 19.5±1.1 K/W with the switch closed.

Empirical Optimization of High Density Plate-Fin Heat Sink for Constant Pumping Power in Low Profile Cooling Application

Since the VLSI processors are increasing power in accordance with exponential law, cooling solutions for such as personal computers have been evolving for over a decade. Recent heat sinks are designed with high dense fins and low profile to adapt to a high heat flux source within a slim enclosure. To achieve such compact cooling solution, thin fin and small gap is desirable. In addition, the pumping power is also limited by the allowable narrow space for fans. Thus it is important to minimize the thermal resistance for given pumping power that we define the optimum. Due to the lack of literatures on topic of low profile and high dense fins experiments, an apparatus was specially built to measure the thermal and fluid dynamic performance at the same time. Since such a high dense fin arrangement requires extra space on the sides by manufacturing reasons, the impact of bypass flow needs to be considered. The experiments are carefully carried out and the results are precisely compared with numerical analysis. The numerical model aiming to find the optimum for given pumping power is discussed with extrapolating the data points. This report is concluded with the best configuration of plate fins of low profile heat sinks for a given fan performance.

The Impact of Varying Feature Dimensions on Substrate Reliability Risks

A sensitivity study is undertaken to characterize the impact of varying feature dimensions in emerging electronic packaging technologies. Specifically, the overall structural performance of the substrate under use conditions (thermal and combined thermomechanical loading) is investigated. The study consists of both modeling and experimental efforts. Modeling approaches are employed within the framework of a finite element code to simulate performance of different design geometry combinations in the known failure mode of solder resist layer cracking. In the models, two levels of complexity are used to better identify the impact of the individual features on the overall substrate reliability. First, local geometry is captured by including each substrate layer. Individual component geometries like microvias and PTHS are also explicitly modeled to capture synergistic failures modes. Second, more realistic non-linear material properties are used to characterize time, temperature, and rate-dependant constitutive behavior of individual substrate materials such as buildup, core, metal, etc. In the experiments, substrate warpage and reliability data is collected for validating the predictive modeling capability. From this study, directions for future design guidelines varying feature dimensions while maintaining substrate reliability are proposed.

Prediction of Microelectronic Substrate Warpage Using Homogenized Thermomechanical Finite Element Models

High-density microelectronic substrates, used in organic CPU packages, are comprised of several polymer, fiber-weave, and copper layers and are filled with a variety of complex features such as traces, micro-vias, Plated-Through-Holes (PTH), and adhesion holes. When subjected to temperature changes, these substrates may warp, driven by the mismatch in Coefficients of Thermal Expansion (CTE) of the constituent materials. This study focused on predicting substrate warpage in an isothermal condition. The numerical approach consisted of three major steps: estimating homogenized (effective) thermomechanical properties of the features; calculating effective properties of discretized layers using the effective properties of the features; and assembling the layers to create 2D Finite Element (FE) plate models and to calculate warpage of the whole substrates. The effective properties of the features were extracted from 3D unit cell FE models, and closed-form approximate expressions were developed using the numerical results, curve fitting, and some simple bounds. The numerical approach was applied to predict warpage of production substrates, analyzed, and validated against experimentally measured stiffness and CTEs. In this paper, the homogenization approach, numerical predictions, and experimental validation are discussed.

A Thermo-Viscoelastic Analysis and Reliability Evaluation for a Single-Sided CSP

In the present paper, a reliability of a single-sided chip-size package (CSP) manufactured using a non-conductive adhesive stud bump direct interconnection method is investigated. The reliability of the CSP is closely related with normal stress between an IC chip and a gold bump. Total normal stress can be decomposed into two parts, deflection related and thermal expansion related. The deflection for a three-layered plate, which is taken into account viscoelastic properties for the resin-sealed sheet and the substrate, respectively, is calculated and compared with experimental results on the deflection of the single-sided CSP. A relationship between the normal stress and the curvature derived from deflection is deduced. Through the use of this relationship, the variation of normal stress with the heat cycle is obtained considering the viscoelastic properties of materials. Furthermore, a relaxation behavior for the thermal stress in the resin-sealed sheet between two rigid walls considering its viscoelastic property is investigated. Summing up normal stresses for each calculation yields the normal stress between the IC and the bump. A relationship between the normal stress and the life of single-sided CSP is investigated for heat cycle. The life in experiment can be explained by the relaxation in the normal stress and the amplitude of the normal stress.