Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)

2013 ◽  
Vol 60 (10) ◽  
pp. 2631-2643 ◽  
Author(s):  
Shin-Kai Chen ◽  
Chih-Wei Liu ◽  
Tsung-Yi Wu ◽  
An-Chi Tsai
Keyword(s):  
Energy Efficient ◽  
High Speed ◽  
Booth Multiplier ◽  
Design And Implementation ◽  
Variable Latency

scholarly journals Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications

2021 ◽  
Vol 9 (12) ◽  
pp. 862-864
Author(s):  
Mutyala Sri Anantha Lakshmi
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Description Language ◽  
Delay Reduction ◽  
Low Area ◽  
Booth Multiplier ◽  
Design And Implementation ◽  
Area Reduction ◽  
Hardware Description ◽  
Very High

Abstract: In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product

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